dramninjasUMD
commented
9 years ago Sorry that these issues have gone unanswered. Since DRAMSim2 typically doesn't store data, we don't model ECC. You could change the bus with to 72 bits and insert a delay in the memory controller to model the latency and data transfer, but there isn't that much value in actually doing ECC computations in a performance simulator in my opinion.
I'm wondering if you have implemented the Error Correcting Code in DRAMSim2? I'm still looking into the codes but it seems to be a huge work to do. I really appreciate it if you can tell me!