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umd-memsys / DRAMSim2

DRAMSim2: A cycle accurate DRAM simulator
http://www.ece.umd.edu/~blj/papers/cal10-1.pdf
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delay calculate bug! #72

Closed Cassiel-girl closed 6 years ago

Cassiel-girl commented 6 years ago

First, The transaction is added in cpu clock.
Source code: transactionReceiver.add_pending(*trans, i); in TraceBasedSim.cpp Second, But the transaction is getted in dram clock. void read_complete(unsigned id, uint64_t address, uint64_t done_cycle) in TraceBasedSim.cpp Third, calculate delay using the two number uint64_t latency = done_cycle - added_cycle; So, Is this correctly? Why not using the same clock？

shavvn commented 6 years ago

all the cycles here are DRAM cycles, so they're the same clock.