Closed smx-smx closed 1 year ago
AFAIK, you can do this by writing to cp regs.
From: smx @.> Sent: Sunday, June 25, 2023 8:16:48 AM To: unicorn-engine/unicorn @.> Cc: Subscribed @.***> Subject: [unicorn-engine/unicorn] aarch64: Fix PSTATE write. Expose CPSR register like on aarch32 (PR #1844)
This makes it possible to change Exception Level correctly (from the default EL1 to EL2 or EL3), and allows to change the processor execution mode (user, monitor, hypervisor, etc..)
Fixes #1843https://github.com/unicorn-engine/unicorn/issues/1843
You can view, comment on, or merge this pull request online at:
https://github.com/unicorn-engine/unicorn/pull/1844
Commit Summary
File Changes
(2 fileshttps://github.com/unicorn-engine/unicorn/pull/1844/files)
Patch Links:
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I tried to, using uc_arm64_cp_reg
, but it didn't work.
I have a program that checks CurrentEL and jumps to an endless loop (halt and catch fire) if not EL3.
Writing uc_arm64_cp_reg
doesn't trigger arm_rebuild_hflags
, therefore the program will still see the old value
Writing
uc_arm64_cp_reg
doesn't triggerarm_rebuild_hflags
, therefore the program will still see the old value
That bug has been fixed here: a24e53d7944110f8a3010436dc0b5bc79cc9776c
Also a fix for aarch32: 75676eb0cd2d7815500dd392d5050e38332c14b9
Closing due to no response and fixed pushed.
This makes it possible to change the Exception Level correctly (from the default EL1 to EL2 or EL3), and allows to change the processor execution mode (user, monitor, hypervisor, etc..)
Fixes #1843