Closed basavesh closed 1 year ago
Test case for PEXT Before Executing
int64_t r_rax = 0x0; // RAX register
int64_t r_rbx = 0x7; // RBX register
int64_t r_rcx = 0x5; // RCX register
Instruction
pext rax,rbx,rcx
After Executing
Emulation done. Below is the CPU context
>>> RAX = 0x5 <--------- wrong
>>> RBX = 0x7
>>> RCX = 0x5
PEXT Intrinsic = 0x3
Fix for PDEP and PEXT. I can create a pull request.
Is it possible that QEMU also has same bug? (didn't test QEMU yet)
diff --git a/qemu/target/i386/translate.c b/qemu/target/i386/translate.c
index b4dc56f2..4a7b0045 100644
--- a/qemu/target/i386/translate.c
+++ b/qemu/target/i386/translate.c
@@ -4226,7 +4226,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
tcg_gen_ext32u_tl(tcg_ctx, s->T1, tcg_ctx->cpu_regs[s->vex_v]);
}
- gen_helper_pdep(tcg_ctx, tcg_ctx->cpu_regs[reg], s->T0, s->T1);
+ gen_helper_pdep(tcg_ctx, tcg_ctx->cpu_regs[reg], s->T1, s->T0);
break;
case 0x2f5: /* pext Gy, By, Ey */
@@ -4244,7 +4244,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} else {
tcg_gen_ext32u_tl(tcg_ctx, s->T1, tcg_ctx->cpu_regs[s->vex_v]);
}
- gen_helper_pext(tcg_ctx, tcg_ctx->cpu_regs[reg], s->T0, s->T1);
+ gen_helper_pext(tcg_ctx, tcg_ctx->cpu_regs[reg], s->T1, s->T0);
break;
case 0x1f6: /* adcx Gy, Ey */
Is it possible that QEMU also has same bug? (didn't test QEMU yet)
Yes, see my comments in your PR
Closed as upstream patch gets backport
I believe the
src
andmask
order is exchanged here while computing the result.PDEP DEST, SRC, MASK
but I think Unicorn is doingPDEP DEST, MASK, SRC
Before Executing:
INSTR:
pdep rax,rbx,rcx
in INTEL syntaxAFTER Executing:
@wtdcode
Repro code: Build cmd:
clang <test_keystone_unicorn.c> -o test_keystone_unicorn -lkeystone -lunicorn -mbmi2