Open TobalJackson opened 1 month ago
I just built the dev branch (2.0.2 - c39e80231c439a6b2231fb47ad02c5057c0d68b6) and re-ran, but received the same error.
Thanks for the reproduction, I will have a look.
I think it is correctly reported as invalid instruction and therefore not a bug.
MRRC
variant is supposed to be 64bit access to coprocessor that implements 64bit registers.
P15 on Cortex-A is "System Control Coprocessor" and all its registers are 32bit wide.
Correct instruction for accessing P15 coprocessor is MRC (32bit access)
something like this MRC p15, 0, r0, c1, c0, 0
Please refer to Cortex-A documentation https://developer.arm.com/documentation/den0013/d/ARM-Processor-Modes-and-Registers/Registers/Coprocessor-15
I did some digging on this subject, and it seems that ARMv7-A added something calle LPAE (Large Physical Address Extension) to support >4GB of ram. In doing so, it seems like there are one or more 64-bit coprocessor registers that were added:
The Large Physical Address Extension, Virtualization Extensions, and the optional Generic Timer introduce a small number of 64-bit control registers.
Yes there are 64bit registers with LPAE (TTBR0 TTBR1 and PAR). https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/About-the-control-registers-for-VMSA/Effect-of-the-LPAE-and-Virtualization-Extensions-on-the-system-control-registers?lang=en
If I change the architecture to Cortex-A15 and try for example PAR register
mrrc p15, 0, r1, r0, c7
it works as expected.
Hello, I've come across an issue with unicorn treating the following instruction as invalid:
the arm documentation describes this instruction as reading a coprocessor register into 2 normal registers: https://developer.arm.com/documentation/dui0489/h/arm-and-thumb-instructions/mrc--mrc2--mrrc-and-mrrc2
Below is an example script which demonstrates this behavior:
And the output:
Please let me know if you'd like additional information, Thank you