Closed 13584452567 closed 1 year ago
the current dtsi doesn't has L1/L2 information,caused error in k8s and some warnings during boot
error in k8s:
failed to get cache information for node 0: open /sys/devices/system/cpu/cpu0/cache: no such file or directory etc ...
warnings in dmesg --level=warn,err
cacheinfo: Unable to detect cache hierarchy for CPU 0
cacheinfo: Unable to detect cache hierarchy for CPU 1
cacheinfo: Unable to detect cache hierarchy for CPU 2
cacheinfo: Unable to detect cache hierarchy for CPU 3
cacheinfo: Unable to detect cache hierarchy for CPU 4
cacheinfo: Unable to detect cache hierarchy for CPU 5
i referred docs below: ARM Cortex-A72 Cache Organization: L1 Cache L2 Cache ARM Cortex-A53 Cache Organization: L1 Cache L2 Cache RockChip RK3399: TRM DataSheet
Changes happens in rk3399.dtsi will affect all dts files based on rk3399.dtsi
I really didn't think it through.I will change my commit and limit changes only in rk3399-eaidk-610.dts
@13584452567 Please provide more information about add L1/L2 cache info
This looks like very low-level code about the CPU. Changes happens in rk3399.dtsi will affect all dts files based on rk3399.dtsi Modifying this file is not a good choose. Can you explain what this patch fixes about?