Closed spdcoding closed 3 years ago
Hi, our preliminary experiments on x86-64 suggest that modeling the architecture with Unison is feasible and not too difficult (including use of memory operands, etc.), see https://github.com/matsc-at-sics-se/unison/blob/master/src/unison/src/Unison/Target/X86.hs. However, Unison's current cost model, devised for simpler in-order architectures, is not accurate enough for speed optimization on x86-64. Refining the cost model would be definitely non-trivial (but interesting).
Wonder the difficulty to apply unison to other CPU architectures which is not mentioned in your papers.