Open DavidCussans opened 7 months ago
Sorry I think I might need a bit of help again here. I know I scribbled something down when we spoke but I can't find the paper. Devices U3/U8 need to be removed, leave U2 for SFP<2>/third SFP.
The newly placed IC3 (854S01) part is to replace "U2" for SFP<2>??
Pete,
Yes, the “issue” doesn’t give much detail.
On two upstream channels remove the D-FF on SFP 0,1 and connect the FPGA directly to the SFP Tx pins:
U8 should be removed and UPSTREAMDATA{P,N}(0) connected directly to SFPTD{P,N}(0) via C106/C100
U3 should be removed and UPSTREAMDATA{P,N}(1) connected directly to SFPTD{P,N}(1) via C101/C98
On the third upstream channel it should be possible to switch between direct connect to the FPGA and connection via a D-FF:
SFPTD{P,N}(2) should be disconnected from U2 and instead connected to the output of multiplexer IC8 ( 854S01 )
One input of IC8 should be connected to the output of U2
For the other input of IC8 there are two choices:
I don’t have a preference for which option is chosen ( 1. or 2. ). Go with the lowest staff cost one. Probably option 1. I guess.
Cheers! David
From: Peter Hastings @.> Sent: Friday, June 21, 2024 2:03 PM To: uob-hep-cad/uob-hep-pc072 @.> Cc: David Cussans @.>; Author @.> Subject: Re: [uob-hep-cad/uob-hep-pc072] Remove D-FF from two upstream SFPs. Add mux to allow either direct or via D-FF on third (Issue #18)
Sorry I think I might need a bit of help again here. I know I scribbled something down when we spoke but I can't find the paper. Devices U3/U8 need to be removed, leave U2 for SFP<2>/third SFP.
The newly placed IC3 (854S01) part is to replace "U2" for SFP<2>??
— Reply to this email directly, view it on GitHubhttps://github.com/uob-hep-cad/uob-hep-pc072/issues/18#issuecomment-2182714307, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ABLNCKRRQEVNXQBDNPEQEXLZIQQA7AVCNFSM6AAAAABAS53F2WVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDCOBSG4YTIMZQG4. You are receiving this because you authored the thread.Message ID: @.**@.>>
Think it is almost done, need your eyes to look at schematic.
Schematic change looks good. Need to double-check that it is OK to connect the "direct out" signal to B16_L14_P/N
The three upstream SFPs can each be connected to a different timing source. Hence return data can't be clocked from same clock.
However, would still like to preserve the ability to have clocking path go direct from clock gen , rather than via FPGA
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