Signals into D-FF U8,U3,U2 all had the same net names ( DFF_CLK_P<0>
etc. ) would have wired all inputs together. Very wrong
One of biasing resistors for D-FF input wasn't connected.
Diff pairs into FPGA connector inverted ( P<--> N ) AUXIO_7 pair ,
DATA_FROMUPSTREAM<1> pair, TIMING.UPSTREAMDATA<2> pair. Pointed
out by Pete Hastings
Connected clocks from Si5495 to FPGA connectors. Show-stopping bug :-o
Fixed connectivity errors
Connected clocks from Si5495 to FPGA connectors. Show-stopping bug :-o
Changed netnames into PLL to clkin_{p,n}<3..0>