Closed Webbah closed 3 years ago
toDo: double check reward function J is not in the range it should be
J over kP:
initial:
different kp:
J should be much (!) smaller! MRE the correct one?
Ideas:
Feedback from the hardware has been extended to include the direction reference values.
Working on obtaining required hardware for current sensor verification.
For Sampling modification, changes to the hardware to choose when to sample and/or to change the internal carrier (forward,reverse, symmetric) are underway.
Using the setpoints from the FPGA hardware seems to solve most of the problems. Turns out calculated SPs (derived from the I_D setpoint and the phase angle) differed significantly.
Second try 1D for ki (kp = 0.01 1/A) current controller layout.
Resulting GP for ki_init = 20 1/(As), lengthscale = 5 /(As):
Initial currents:
"Best" Result for ki = 11.7 /(As):
toDo:
great intermediate result! nice progress
quick question on the current waveforms: it seems that the three phase current is not idea, even in steady state (e.g. blue current is always too large for negative peak and green current is always too low for positive peak values). did you run an offset and gain compensation for all three current sensors before runing the experiment? Or do you have other ideas where the asymmetry / harmonics is coming from?
It seems to stem from an unbalanced filter inductance, especially in a short circuit and with low V_dc values.
DQ0 control struggles with this. We do see the imbalanced currents in the verification probes. So I do not think it is an error with the measurement circuit.
Intermediate result in 2D (x->kp, y->ki; interrupted by ss connection error)
initial:
currently best one (green dot, first pic)
Very nice result for 2D optimization. Here also the asymmetry is mostly gone -> interesting.
Second try, higher lentghscale (reaches unsafe point (kP=0 in plot below), but with less results more exploration...)
Yes, also first thought maybe tuning... but unbalanced L the case, too....
Comparison for same tuning of the current controller, showing only current through phase a at the moment
error(kP,kI) landscape from testbench Due to visibility, the z-values are limited to 390
Plan: Controller layout in simulation (Pt1 -> RL & Pt1 -> Inverter), Magnitude Optimum -> Kp&Ki_init Estimate maximum lengthscale -> Use for measurement
Voltage Controller -> same
Apply loadsteps; wait for steady state -> full load -> half load
Idea to make the simulation model becomer closer to reality: add white noise to the current (and voltage) 'measurements' within the Python interface to the OM-FMU container. mean = zero Variance = take a snapshot time period from the test bench with actively swichting transistors controling a zero current / zero voltage. the measured signals can be then assumed to be the pure noise component and used to estimate the variance of the noise process.
Issue with sensor overcurrent is likely an underperforming op-amp.
Sensor uses a transimpedance amplifier to convert the current output (25mA nominal) from LEM LAH 25-NP (which has a 1:1000 conversion ratio). The op-amp (TL082) only has a 20mA maximum source/sink.
Options:
Investigating option 1 at the moment.
Noise measurement for current measurements from testbench: max(standard deviation) of 0.11 A detected
At the moment len(obs)*std(noide_measurement) is taken. For voltage control that has to be adjusted
Adjusted the current sensors using option 2 as mentioned above. Different gains for system (3.6A/V to 6A/V).
But we can now have currents over 30A without non-linear behaviour
Current controller layout using safeopt - Testbench
(y-axis: lengthscale for kp, x-axis: lengthscale for ki; green -> safe; blue circle -> chosen point for measurement; can do picture more beautiful later )
Result:
Initial controller tune: (Title: Performance value)
Best result Kpi = [0.9626728565572376, 24.507337238803796] (green circle in the agent plot above) Performance increase by 11.58 % But more noise on it, run for longer? Weight the initial error less or the "later" error ('noise' around the setpoint) higher? So slower step response but less noise?
First try with voltage controller running on open circuit using analytical current controller layout results.
Initial result (without analytical layout): (Performance in the title)
ylabel = v_abc / V!!! Corrected for the next runs!
Best result after 100 epsiodes: ylabel = v_abc / V!!! Corrected for the next runs!
Are the following stuff results from the test bench or simulation? Was not 100 % sure from your text input.
Answer: From Testbench
Best result Kpi = [0.9626728565572376, 24.507337238803796] (green circle in the agent plot above) Performance increase by 11.58 % But more noise on it, run for longer? Weight the initial error less or the "later" error ('noise' around the setpoint) higher? So slower step response but less noise?
Regarding the noise in steady-state: Did you use the mean root error (MRE) as the cost criterion (as in the preprint paper) or something different? Normaly the MRE is quite a suitable cost function to ensure nice behavior in steady-state since smaller control errors are not squeezed-together compared to the standard MSE. Nevertheless, with respect to the results the noise amount is increased, yes, but with the initial controller parameters there was also some significant harmonics on the current which are suppressed with the optimal tuning design.
Just double checked: For the reward, the same function was used as in the paper - so MRE + Barrier
Additional question regarding the current controller results: How close are not the behavior from the simulation and the experimental optimization? Is the performance landscape and the optimal found controller gains both similar in simulation and experiment?
This is simulation
Initial episode: J = 1
Best episode: J = 1.25
Issue with sensor overcurrent is likely an underperforming op-amp.
Sensor uses a transimpedance amplifier to convert the current output (25mA nominal) from LEM LAH 25-NP (which has a 1:1000 conversion ratio). The op-amp (TL082) only has a 20mA maximum source/sink.
Options:
Investigating option 1 at the moment.
Additional question: how the the DC-voltage behaving during the start-up phase? Is it still a perfect constant voltage (as modeled within OMG) or do we see a significant dip during the start up?
I have checked the DC-Link behaviour of the system during the open-circuit and short circuit tests. Here are the waveforms Orange is the VDC bus (AC Coupled), the bottom display is the currents or voltages. Under short circuit (first 100ms of DC bus noise is with no modulation, performing a current nulling test).
Under open circuit
I do not get the voltage measurement. I would expect to see the average DC-link voltage (at around 60 V?) and then some ripple and a possible dip (when starting the current control) on top. Assuming that above the orange signal is the DC-bus, why it is around 0 V?
Orange is the VDC bus (AC Coupled), the bottom display is the currents or voltages.
Note, this measurement was taken using the custom voltage sensors. I will test it soon with an independant differential probe.
Repeated short circuit test, but with 2 sensors for the VDC (Given here in absolute units).
results in paper, branch mereg to develop
Test setup: single inverter connected to RL (0.5 ohm, 2m2H). Parameter tuning using safeopt