QuestaSim does not allow continuous assignment to a reg found in `modify_instruction.v`

[eldrickm]

Issue

The generator outputs modify_instruction.v which contains the following lines:

output reg [31:0] qed_instruction;
...
assign qed_instruction = ...;

In QuestaSim vlog compiler, an error occurs when trying to continuously assign a value to a reg.

Error trace given below:

[steelcore_demo]>>make design
========== Intializing Questa Workspace ==========
/cad/mentor/qformal/linux_x86_64/modeltech/plat/vlib work
/cad/mentor/qformal/linux_x86_64/modeltech/plat/vmap work work
QuestaSim-64 vmap 10.5c Lib Mapping Utility 2016.07 Jul 20 2016
vmap work work
Copying /hd/cad/mentor/qformal/share/modeltech/linux_x86_64/../modelsim.ini to modelsim.ini
Modifying modelsim.ini
mkdir -p output
========== Compiling Design ==========
./patches/patch.sh
/cad/mentor/qformal/linux_x86_64/modeltech/plat/vlog -f design/design.flist -f formal/formal.flist -l output/vlog.rpt
QuestaSim-64 vlog 10.5c Compiler 2016.07 Jul 20 2016
Start time: 11:31:43 on Mar 28,2021
vlog -f design/design.flist -f formal/formal.flist -l output/vlog.rpt
-- Compiling module alu
-- Compiling module branch_unit
-- Compiling module csr_file
-- Compiling module decoder
-- Compiling module design_top
-- Compiling module imm_generator
-- Compiling module integer_file
-- Compiling module load_unit
-- Compiling module machine_control
-- Compiling module ram
-- Compiling module steel_top
-- Compiling module store_unit
-- Compiling module inst_constraint
-- Compiling module modify_instruction
** Error: ./qed/modify_instruction.v(70): Register is illegal in left-hand side of continuous assignment
-- Compiling module qed_decoder
-- Compiling module qed_i_cache
-- Compiling module qed_instruction_mux
-- Compiling module qed
-- Compiling module formal_spec
-- Compiling module formal_bind
End time: 11:31:44 on Mar 28,2021, Elapsed time: 0:00:01
Errors: 1, Warnings: 0
make: *** [design] Error 2

With the particular error in question being:

-- Compiling module modify_instruction
** Error: ./qed/modify_instruction.v(70): Register is illegal in left-hand side of continuous assignment

Potential Fix

Simply removing the reg identifier in the declaration of qed_instruction allows compilation with QuestaSim vlog Compiler.

output [31:0] qed_instruction;
...
assign qed_instruction = ...;

[lonsing]

Thanks for bringing this up!

Actually, Yosys issues a similar warning but still processes the design without error:

Warning: reg '\qed_instruction' is assigned in a continuous assignment at ./sqed-generator/SQED-Generator/QEDFiles/modify_instruction.v:70.10-70.119.

[lonsing]

This issue is related to https://github.com/upscale-project/sqed-generator/issues/4