Added HIP support for new scikit-build-core driven compilation to support AMD machines.
Runahead scheduling bugs still exist here, but ..are shared between CUDA and HIP. They will be fixed in a followup PR.
Everything should be working for non-runahead and via CuPy.
Be aware that CuPy does not support sparse CUSOLVER routines with ROCm and our initialization skips this preinit step.
On Cray systems you may need to add cce libraries to your LIBRARY_PATH manually. I haven't been able to resolve this automatically on Tioga.
On TIOGA you may need to filter HIP_VISIBLE_DEVICES to 0,2,4,6.
Added HIP support for new scikit-build-core driven compilation to support AMD machines.
Runahead scheduling bugs still exist here, but ..are shared between CUDA and HIP. They will be fixed in a followup PR.
Everything should be working for non-runahead and via CuPy. Be aware that CuPy does not support sparse CUSOLVER routines with ROCm and our initialization skips this preinit step.
On Cray systems you may need to add cce libraries to your LIBRARY_PATH manually. I haven't been able to resolve this automatically on Tioga. On TIOGA you may need to filter HIP_VISIBLE_DEVICES to 0,2,4,6.