OBC PCB iteration

[vogeldylan]

Reference #4 #22 and outcomes from #26

[vogeldylan]

Waiting on #27

[brunofalmeida]

@hirolemo

• Replace 32M1 and CAN transceiver sheets with the ones from pcbs-common (see the EPS board for an example of how to do it)
• Integrate the backup battery for RTC when @jadenreimer is done selecting it
• Should number the flash memories 0-2 instead of 1-3
• Let's talk on Tuesday to clean up the file names
• Should start layout ASAP (I can help if you want)

[brunofalmeida]

@hirolemo note the new EPS-OBC header connections in the systems wiring diagram v0.5

[vogeldylan]

OBC Review

1. Linked pcbs-common schematics into the existing OBC project. Had to make a couple of changes:
   • Added a couple more no-erc's to suppress some sheet entry errors (mostly bi-directional<-> output)
   • Synchronized sheet entries
   • Had some issue with 1206 caps appearing on the flash schematic, just updated those to 0603 since it looks like you already routed them.
   • Was some issue with missing one of the I2C 0 ohm jumpers. Fixed by just adding the trace that I wired up
2. Would be better to specify 100 ohm instead of 1K current limiting resistors. 1K is fairly weak.
3. Don't put your silkscreen over component pads. Also, change your component designators to Stroke from TrueType. If you feel tight on space, for context I've used 0.75mm height, 0.2mm stroke width component designators before on PAY-Optical and they look fine. Might help you fit them. Be sure to select all the text on your board at once and bulk-change the designators, instead of going one-by-one.
4. These debugging labels won't work. Try putting them horizontal, and alternating top/bottom for the label. For the power lines on the right, just use one label for both pins to dodge the crystal. The smaller labels I recommended might help.
5. Where you can, I'd just recommend throwing vias inside the GND pads to reduce the inductance of your GND connection. Shouldn't impact soldering since we're not soldering the butterfly connectors. In fact, being able to put via-in-pad for your entire butterfly connector is something you could make use of to save space elsewhere, if needed.
6. If you really want to make use of local ground planes for your crystal, add small rectangular copper keepouts on your global ground plane around your crystal GND connections, as shown below. This will stop noise from traveling along your global GND plane to reach the 32M1 GND. I did not commit this change, just drew it for FYI
7. You can remove this corner of your 32M1 GND pour. This unconnected section doesn't do anything.
8. Here I've highlighted your PAY net, which connects to the 1K current-limiting resistor I mentioned in (2), which then just connects to RST PAY and goes to the butterfly. Nothing wrong with this trace routing per-say, but better planning might have allowed you to route this and EPS RST together with other signals going to the butterfly header in a bus, rather than the circuitous path you're taking now. Also, avoid those 90 deg angles on you traces.
9. Would just connect the top-layer traces through the via and avoid this weird routing
10. You've gone well out of your way to route this 1K pull-up for the RTC Interrupt pin. The signal itself comes out of the top of the 32M1, which you then extend down just to connect the resistor. Again, nothing wrong with this per-say, but better planning would throw that 1K somewhere along the main trace between 32M1<->RTC
11. Add a pull-up to any CSn pin. Someone writing software is bound to leave that 32M1 GPIO uninitialized as input when writing tests for another component, which could cause the RTC to listen/interfere with other SPI communications. A small change to save someone potentially hours of debugging.
12. As per the RTC datasheet, you should add something like a 0.1uF bypass cap between VCC and GND. Also, A more typical value for the INTn/SQW pull-up would be 10K, although 1K is probably fine. The 1K just forces more current to be sunk through the INTn/SQW pin. Taking a quick look through the datasheet, it seems like the pins can handle 1.0 mA, although I don't see any maximum current sink capability given. 3V3/1K = 3.3mA; a little high, perhaps.
13. Nope
14. This voltage-level translator has been wired incorrectly, and will not work. Refer to Section 9 of the datasheet for a typical application circuit. Also read through the sections on pull-up resistor sizing to select those values. Endurosat UHF Antenna datasheet seems to suggest 4.7K pull-ups, but I'd still read through the datasheet to understand what's going on.
15. This SPI to I2C bridge could also use some pull-ups/down and bypassing caps. As per datasheet, INTn is open-drain so you'll need a pull-up resistor to use it. I'd also recommend adding a pull-down to WAKEUPn if you want the device default ON, or a pull-up if you want it default OFF. Add a pull-up resistor to CSn. RSNn has an internal pull-up resistor, so you're OK there. Good to check though.
16. Again, 1K is probably a little small for the CS pull-up. I'd change it to 10k. 100pF is also pretty small for a bypass cap. 0.1uF would be a more normal size. The 1K's and 100pF's look a bit like the default resistor and capacitor values in Altium. If you want a better explanation of why we use 10K, check out this electrical engineering stack exchange question: https://electronics.stackexchange.com/questions/23645/how-do-i-calculate-the-required-value-for-a-pull-up-resistor/23647#23647 I couldn't find a nice explanation for why 0.1uF is a nice value, but you can read this post for an overview of what bypassing is doing: https://electronics.stackexchange.com/questions/15135/decoupling-caps-pcb-layout/15143#15143
17. You have some space, so I would move the TRANS EN UHF via up and tie all the GND pins together as directly as possible.
18. Your common-mode filter cap is also pretty far away from the 60 ohm termination resistors. Move it between them for better filtering.
19. Any GND or 3V3 component holes are internally tied to the internal 3V3 and GND pours. No need to route little traces and vias.
20. Same thing here
21. Overall, your component placement and layout seem ok. Would just use the lessons you've learned from this process to make the flight model neater and more compact.

[brunofalmeida]

A couple of things @hirolemo :

1. Need to implement the open-drain buffer you selected for the RTC RST, I think this will take the last GPIO pin on the 32M1 so LED1 will be renamed
2. It would be easier for testing/debugging if the PGM <-> RUN switch was facing outwards (but make sure mechanically the switch doesn't extend past the edge of the board)
3. Silkscreen - need to label RST button, PGM <-> RUN switch, TX/RX for UART

[brunofalmeida]

Review - Part 1

1. See my last comment, points 2 and 3

2. PGM label is overlapping (there are other labels overlapping or upside-down but I assume this was intentionally left to deal with later)

[brunofalmeida]

Review - Part 2

1. Can we have a 5V pin on the debugging header? Would be useful for debugging I2C if it turns out to be 5V. I'm not sure if it would be better to replace something or add an extra pin. @vogeldylan what do you think?

2. Label the RST button

3. RX and TX text should be on the same side (right or left)

4. I'm confused about the LED labelling here (UHF and TUHF). This is supposed to be for TRANS_EN_UHF and TRANS_EN_UHF_OPT right? Maybe something like UHF and UHF_OPT?

[brunofalmeida]

Update on point 1: should replace a 3V3 on the debugging header with 5V

[vogeldylan]

See f99734c9bcc0b62879bd54d5f71784b96560c67c