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Unified Verification Environment
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Adding Verilog/SV RTL support in UVE #15

Open svenka3 opened 8 years ago

svenka3 commented 8 years ago

As far as I see UVE supports VHDL DUT. This is cool, but there are quite a few other half engineers using Verilog/SV for RTL. I am willing to put in effort to make that happen if needed.

Thanks Srini www.go2uvm.org

ythoma commented 8 years ago

Currently there is a bison/flex parser that is used to parse the VHDL file and find the entity and its ports. It is a little bit overkill as we only need the entity and its ports, nothing more. It could be quite easy to add new parsers. You can have a look at line 244 of newprojectwizard.cpp. This is where a VHDL parser is used to generate a VHDLFileContent. Here we could choose a Verilog of SV parser based on the file type. The only requirement is that the parser should generate the fields of VHDLFileContent. Please feel free to work on that part. :-)