If Verilog variables include keywords - it'll cause an Egglog syntax error. - Githubissues

uwsampl / churchroad

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If Verilog variables include keywords - it'll cause an Egglog syntax error. #61

Open thiskappaisgrey opened 4 weeks ago

thiskappaisgrey commented 4 weeks ago

For example, if you have: (let set (Var "set" 1))

This is an Egglog syntax error.