Generate examples of Lakeroad+Yosys integration used in bigger projects

[gussmith23]

From @nakengelhardt:

That's here: https://github.com/nakengelhardt/fpgagraphlib for the pagerank/"pr" example specifically (not sure how easy this is to use/run if you haven't written the code, I can export the verilog for a specific configuration for you if you want)

[gussmith23]

Doing some searching with GitHub's codesearch. I'm finding a lot of instances where people use DSPs directly, or use the use_dsp annotation. Less obvious are the cases where they have a module that should go onto a DSP.

[gussmith23]

Maybe this? https://github.com/hzeller/ibex/blob/416ecb10dfdb80ce88b8b41ab7c39a6bcefbba50/rtl/ibex_counter.sv#L4

[gussmith23]

Unsure what this does, but this could be one: https://github.com/snu-quiqcl/RFSoC/blob/79dadb5c0f81f8f9d77530b08ecb28077aab6ce1/RFSoC_Design_V1_1/IP_File_00/DAC_Controller/RFDC_DDS.sv#L40

[gussmith23]

Stopped on page three here, should pick it up later: https://github.com/search?q=DSp+xilinx+language%3ASystemVerilog&type=code&p=3