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Lakeroad's 1-bit workloads failing Verilator tasks #114

Open ninehusky opened 9 months ago

ninehusky commented 9 months ago

cc @gussmith23

While synthesis passes the following workloads, the Verilator tasks give the following error:

testbench: /home/acheung8/lakeroad-evaluation/out/robustness_experiments/muladd_3_stage_signed_1_bit/lakeroad_xilinx_ultrascale_plus/verilator/testbench.cc:113: int main(int, char**): Assertion `test_module->out == ground_truth_module->out' failed.
Aborted (core dumped)
make: *** [/home/acheung8/lakeroad-evaluation/out/robustness_experiments/muladd_3_stage_signed_1_bit/lakeroad_xilinx_ultrascale_plus/verilator/Makefile:9: simulate] Error 134

This is the case for several 1-bit workloads:

ninehusky commented 9 months ago

I'll attach the code for each workload's corresponding lakeroad-result.sv file here:

mulsub_3_stage_unsigned_1_bit.sv:

/* Generated by Yosys 0.32+66 (git sha1 2f901a829, clang 10.0.0-4ubuntu1 -fPIC -Os) */

module \output (a, b, c, clk, out);
  wire [47:0] P_0;
  input a;
  wire a;
  input b;
  wire b;
  input c;
  wire c;
  input clk;
  wire clk;
  output out;
  wire out;
  DSP48E2 #(
    .ACASCREG(32'd0),
    .ADREG(32'd0),
    .ALUMODEREG(32'd0),
    .AMULTSEL("AD"),
    .AREG(32'd0),
    .AUTORESET_PATDET("NO_RESET"),
    .AUTORESET_PRIORITY("RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(32'd0),
    .BMULTSEL("B"),
    .BREG(32'd0),
    .B_INPUT("DIRECT"),
    .CARRYINREG(32'd0),
    .CARRYINSELREG(32'd0),
    .CREG(32'd0),
    .DREG(32'd0),
    .INMODEREG(32'd1),
    .IS_ALUMODE_INVERTED(4'h0),
    .IS_CARRYIN_INVERTED(1'h0),
    .IS_CLK_INVERTED(1'h0),
    .IS_INMODE_INVERTED(5'h00),
    .IS_OPMODE_INVERTED(9'h000),
    .IS_RSTALLCARRYIN_INVERTED(1'h0),
    .IS_RSTALUMODE_INVERTED(1'h0),
    .IS_RSTA_INVERTED(1'h0),
    .IS_RSTB_INVERTED(1'h0),
    .IS_RSTCTRL_INVERTED(1'h0),
    .IS_RSTC_INVERTED(1'h0),
    .IS_RSTD_INVERTED(1'h0),
    .IS_RSTINMODE_INVERTED(1'h0),
    .IS_RSTM_INVERTED(1'h0),
    .IS_RSTP_INVERTED(1'h0),
    .MASK(48'h000000000000),
    .MREG(32'd0),
    .OPMODEREG(32'd0),
    .PATTERN(48'h000000000000),
    .PREADDINSEL("A"),
    .PREG(32'd1),
    .RND(48'h000000000000),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48"),
    .USE_WIDEXOR("FALSE"),
    .XORSIMD("XOR12")
  ) DSP48E2_0 (
    .A({ 29'h00000000, a }),
    .ACIN(30'h00000000),
    .ALUMODE(4'h2),
    .B({ 17'h00000, b }),
    .BCIN(18'h00000),
    .C({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .CARRYCASCIN(1'h0),
    .CARRYIN(1'h0),
    .CARRYINSEL(3'h6),
    .CEA1(1'h1),
    .CEA2(1'h1),
    .CEAD(1'h1),
    .CEALUMODE(1'h1),
    .CEB1(1'h1),
    .CEB2(1'h1),
    .CEC(1'h1),
    .CECARRYIN(1'h1),
    .CECTRL(1'h1),
    .CED(1'h1),
    .CEINMODE(1'h1),
    .CEM(1'h1),
    .CEP(1'h1),
    .CLK(clk),
    .D({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .INMODE(5'h16),
    .MULTSIGNIN(1'h0),
    .OPMODE(9'h12d),
    .P({ P_0[47:1], out }),
    .PCIN(48'h000000000000),
    .RSTA(1'h0),
    .RSTALLCARRYIN(1'h0),
    .RSTALUMODE(1'h0),
    .RSTB(1'h0),
    .RSTC(1'h0),
    .RSTCTRL(1'h0),
    .RSTD(1'h0),
    .RSTINMODE(1'h0),
    .RSTM(1'h0),
    .RSTP(1'h0)
  );
  assign P_0[0] = out;
endmodule
ninehusky commented 9 months ago

mulsub_3_stage_signed_1_bit.sv:

/* Generated by Yosys 0.32+66 (git sha1 2f901a829, clang 10.0.0-4ubuntu1 -fPIC -Os) */

module \output (a, b, c, clk, out);
  wire [47:0] P_0;
  input a;
  wire a;
  input b;
  wire b;
  input c;
  wire c;
  input clk;
  wire clk;
  output out;
  wire out;
  DSP48E2 #(
    .ACASCREG(32'd0),
    .ADREG(32'd0),
    .ALUMODEREG(32'd0),
    .AMULTSEL("AD"),
    .AREG(32'd0),
    .AUTORESET_PATDET("NO_RESET"),
    .AUTORESET_PRIORITY("RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(32'd0),
    .BMULTSEL("B"),
    .BREG(32'd0),
    .B_INPUT("DIRECT"),
    .CARRYINREG(32'd0),
    .CARRYINSELREG(32'd0),
    .CREG(32'd0),
    .DREG(32'd0),
    .INMODEREG(32'd1),
    .IS_ALUMODE_INVERTED(4'h0),
    .IS_CARRYIN_INVERTED(1'h0),
    .IS_CLK_INVERTED(1'h0),
    .IS_INMODE_INVERTED(5'h00),
    .IS_OPMODE_INVERTED(9'h000),
    .IS_RSTALLCARRYIN_INVERTED(1'h0),
    .IS_RSTALUMODE_INVERTED(1'h0),
    .IS_RSTA_INVERTED(1'h0),
    .IS_RSTB_INVERTED(1'h0),
    .IS_RSTCTRL_INVERTED(1'h0),
    .IS_RSTC_INVERTED(1'h0),
    .IS_RSTD_INVERTED(1'h0),
    .IS_RSTINMODE_INVERTED(1'h0),
    .IS_RSTM_INVERTED(1'h0),
    .IS_RSTP_INVERTED(1'h0),
    .MASK(48'h000000000000),
    .MREG(32'd0),
    .OPMODEREG(32'd0),
    .PATTERN(48'h000000000000),
    .PREADDINSEL("A"),
    .PREG(32'd1),
    .RND(48'h000000000000),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48"),
    .USE_WIDEXOR("FALSE"),
    .XORSIMD("XOR12")
  ) DSP48E2_0 (
    .A({ 29'h00000000, a }),
    .ACIN(30'h00000000),
    .ALUMODE(4'h2),
    .B({ 17'h00000, b }),
    .BCIN(18'h00000),
    .C({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .CARRYCASCIN(1'h0),
    .CARRYIN(1'h0),
    .CARRYINSEL(3'h6),
    .CEA1(1'h1),
    .CEA2(1'h1),
    .CEAD(1'h1),
    .CEALUMODE(1'h1),
    .CEB1(1'h1),
    .CEB2(1'h1),
    .CEC(1'h1),
    .CECARRYIN(1'h1),
    .CECTRL(1'h1),
    .CED(1'h1),
    .CEINMODE(1'h1),
    .CEM(1'h1),
    .CEP(1'h1),
    .CLK(clk),
    .D({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .INMODE(5'h16),
    .MULTSIGNIN(1'h0),
    .OPMODE(9'h12d),
    .P({ P_0[47:1], out }),
    .PCIN(48'h000000000000),
    .RSTA(1'h0),
    .RSTALLCARRYIN(1'h0),
    .RSTALUMODE(1'h0),
    .RSTB(1'h0),
    .RSTC(1'h0),
    .RSTCTRL(1'h0),
    .RSTD(1'h0),
    .RSTINMODE(1'h0),
    .RSTM(1'h0),
    .RSTP(1'h0)
  );
  assign P_0[0] = out;
endmodule
ninehusky commented 9 months ago

muladd_3_stage_unsigned_1_bit.sv:

/* Generated by Yosys 0.32+66 (git sha1 2f901a829, clang 10.0.0-4ubuntu1 -fPIC -Os) */

module \output (a, b, c, clk, out);
  wire [47:0] P_0;
  input a;
  wire a;
  input b;
  wire b;
  input c;
  wire c;
  input clk;
  wire clk;
  output out;
  wire out;
  DSP48E2 #(
    .ACASCREG(32'd0),
    .ADREG(32'd0),
    .ALUMODEREG(32'd0),
    .AMULTSEL("AD"),
    .AREG(32'd0),
    .AUTORESET_PATDET("NO_RESET"),
    .AUTORESET_PRIORITY("RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(32'd0),
    .BMULTSEL("B"),
    .BREG(32'd0),
    .B_INPUT("DIRECT"),
    .CARRYINREG(32'd0),
    .CARRYINSELREG(32'd0),
    .CREG(32'd0),
    .DREG(32'd0),
    .INMODEREG(32'd1),
    .IS_ALUMODE_INVERTED(4'h0),
    .IS_CARRYIN_INVERTED(1'h0),
    .IS_CLK_INVERTED(1'h0),
    .IS_INMODE_INVERTED(5'h00),
    .IS_OPMODE_INVERTED(9'h000),
    .IS_RSTALLCARRYIN_INVERTED(1'h0),
    .IS_RSTALUMODE_INVERTED(1'h0),
    .IS_RSTA_INVERTED(1'h0),
    .IS_RSTB_INVERTED(1'h0),
    .IS_RSTCTRL_INVERTED(1'h0),
    .IS_RSTC_INVERTED(1'h0),
    .IS_RSTD_INVERTED(1'h0),
    .IS_RSTINMODE_INVERTED(1'h0),
    .IS_RSTM_INVERTED(1'h0),
    .IS_RSTP_INVERTED(1'h0),
    .MASK(48'h000000000000),
    .MREG(32'd0),
    .OPMODEREG(32'd0),
    .PATTERN(48'h000000000000),
    .PREADDINSEL("A"),
    .PREG(32'd1),
    .RND(48'h000000000000),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48"),
    .USE_WIDEXOR("FALSE"),
    .XORSIMD("XOR12")
  ) DSP48E2_0 (
    .A({ 29'h00000000, a }),
    .ACIN(30'h00000000),
    .ALUMODE(4'h2),
    .B({ 17'h00000, b }),
    .BCIN(18'h00000),
    .C({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .CARRYCASCIN(1'h0),
    .CARRYIN(1'h0),
    .CARRYINSEL(3'h6),
    .CEA1(1'h1),
    .CEA2(1'h1),
    .CEAD(1'h1),
    .CEALUMODE(1'h1),
    .CEB1(1'h1),
    .CEB2(1'h1),
    .CEC(1'h1),
    .CECARRYIN(1'h1),
    .CECTRL(1'h1),
    .CED(1'h1),
    .CEINMODE(1'h1),
    .CEM(1'h1),
    .CEP(1'h1),
    .CLK(clk),
    .D({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .INMODE(5'h16),
    .MULTSIGNIN(1'h0),
    .OPMODE(9'h12d),
    .P({ P_0[47:1], out }),
    .PCIN(48'h000000000000),
    .RSTA(1'h0),
    .RSTALLCARRYIN(1'h0),
    .RSTALUMODE(1'h0),
    .RSTB(1'h0),
    .RSTC(1'h0),
    .RSTCTRL(1'h0),
    .RSTD(1'h0),
    .RSTINMODE(1'h0),
    .RSTM(1'h0),
    .RSTP(1'h0)
  );
  assign P_0[0] = out;
endmodule
ninehusky commented 9 months ago

muladd_3_stage_signed_1_bit.sv

/* Generated by Yosys 0.32+66 (git sha1 2f901a829, clang 10.0.0-4ubuntu1 -fPIC -Os) */

module \output (a, b, c, clk, out);
  wire [47:0] P_0;
  input a;
  wire a;
  input b;
  wire b;
  input c;
  wire c;
  input clk;
  wire clk;
  output out;
  wire out;
  DSP48E2 #(
    .ACASCREG(32'd0),
    .ADREG(32'd0),
    .ALUMODEREG(32'd0),
    .AMULTSEL("AD"),
    .AREG(32'd0),
    .AUTORESET_PATDET("NO_RESET"),
    .AUTORESET_PRIORITY("RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(32'd0),
    .BMULTSEL("B"),
    .BREG(32'd0),
    .B_INPUT("DIRECT"),
    .CARRYINREG(32'd0),
    .CARRYINSELREG(32'd0),
    .CREG(32'd0),
    .DREG(32'd0),
    .INMODEREG(32'd1),
    .IS_ALUMODE_INVERTED(4'h0),
    .IS_CARRYIN_INVERTED(1'h0),
    .IS_CLK_INVERTED(1'h0),
    .IS_INMODE_INVERTED(5'h00),
    .IS_OPMODE_INVERTED(9'h000),
    .IS_RSTALLCARRYIN_INVERTED(1'h0),
    .IS_RSTALUMODE_INVERTED(1'h0),
    .IS_RSTA_INVERTED(1'h0),
    .IS_RSTB_INVERTED(1'h0),
    .IS_RSTCTRL_INVERTED(1'h0),
    .IS_RSTC_INVERTED(1'h0),
    .IS_RSTD_INVERTED(1'h0),
    .IS_RSTINMODE_INVERTED(1'h0),
    .IS_RSTM_INVERTED(1'h0),
    .IS_RSTP_INVERTED(1'h0),
    .MASK(48'h000000000000),
    .MREG(32'd0),
    .OPMODEREG(32'd0),
    .PATTERN(48'h000000000000),
    .PREADDINSEL("A"),
    .PREG(32'd1),
    .RND(48'h000000000000),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48"),
    .USE_WIDEXOR("FALSE"),
    .XORSIMD("XOR12")
  ) DSP48E2_0 (
    .A({ 29'h00000000, a }),
    .ACIN(30'h00000000),
    .ALUMODE(4'h2),
    .B({ 17'h00000, b }),
    .BCIN(18'h00000),
    .C({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .CARRYCASCIN(1'h0),
    .CARRYIN(1'h0),
    .CARRYINSEL(3'h6),
    .CEA1(1'h1),
    .CEA2(1'h1),
    .CEAD(1'h1),
    .CEALUMODE(1'h1),
    .CEB1(1'h1),
    .CEB2(1'h1),
    .CEC(1'h1),
    .CECARRYIN(1'h1),
    .CECTRL(1'h1),
    .CED(1'h1),
    .CEINMODE(1'h1),
    .CEM(1'h1),
    .CEP(1'h1),
    .CLK(clk),
    .D({ c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c, c }),
    .INMODE(5'h16),
    .MULTSIGNIN(1'h0),
    .OPMODE(9'h12d),
    .P({ P_0[47:1], out }),
    .PCIN(48'h000000000000),
    .RSTA(1'h0),
    .RSTALLCARRYIN(1'h0),
    .RSTALUMODE(1'h0),
    .RSTB(1'h0),
    .RSTC(1'h0),
    .RSTCTRL(1'h0),
    .RSTD(1'h0),
    .RSTINMODE(1'h0),
    .RSTM(1'h0),
    .RSTP(1'h0)
  );
  assign P_0[0] = out;
endmodule
gussmith23 commented 9 months ago

This may be fixed once we update Bitwuzla in https://github.com/uwsampl/lakeroad/pull/365 and then resolve #115