Sm asic flow - Githubissues

Added unit test for stratix III like dsp from COFFE 2 paper, some csv/plotting scripts, removed aboslute paths from config files, updated user guide, updated primetime scripts, power analysis for DC 2017

The way I tested the strtatix_III_dsp block was by going to the ASIC flow section in the User Guide and following the instructions: https://github.com/vaughnbetz/COFFE/pull/35/files#diff-2f8534d3cafa5add9da1f0f7c12f787561c64b9e551d79c78aab52f83065b545R36

Overview

Improvements in parsing hardblock configuration data, refactoring in hardblock functions, minor changes to synthesis,power, timing scripts.

Specific Changes

Utility

Improved the parsing of hardblock parameters from config file
Added preprocessing function for formatting hb params before they get written to tcl scripts
Allow for users to input the "process_specific_params_file" parameter in the hardblock parameter file, this is for absolute paths to .lib, .lef, and .db files as well as any parameter which relies on values inside of such files. Users can still input the same parameters through the hardblock file so it shouldn't break other flows but in the future one could have multiple process specific param files and keep the arch and hb_params file the same when testing the same design across multiple process nodes.

Asic Flow

-In preprocessing function the "search_path" for both primetime and synthesis scripts is generated (which replaces the "primetime_lib_path" parameter). It derives its search path from the SYNOPSYS environment variable which should be set DC is properly setup. After adding the inital synopsys directories the process libs and verilog source directories are added as well.

refactored asic stages to have seperate functions for writing tcl scripts and running them / reading in results and specifying the hb params in which it was run under
each asic flow stage now copies the result files (tcl scripts, logs, reports) to a unique directory
removed "link_libraries" parameter now the link_libaries for both power and synthesis are set to the value of "* $target_libraries" which is equivalent to the flow before (and I believe is good practice moving forward)
modified the "set_switching_activity" command in power script to use "-baseClk $my_clock_pin -type inputs " instead of the [all_nets] command, as it wasn't supported in DC 2017.
changed hb param "primetime_lib_name" into "primetime_libs" (same format as other strings taken in as lists)

Unit Test & Post Processing

Added Sadeghs old dsp verilog code used for results in COFFE 2 paper, along with hb_settings file which includes the configurations to run it on UofT servers on tsmc 65nm process
Added utility script which allow for reports to be condensed to a single csv file
Added utility script to take condensed csv and create plots for delay, area, power, cost (area x delay) vs achieved freq
Added small unit_test script which runs the whole flow and then the previously mentioned utility script

Testing procedure

Note: I couldn't get any accurate power/delay results from the primetime scripts until I made the set_switching_activity change so my inital results were after that command was changed, however, the rest of the scripts in coffe stayed the same.

Ran the COFFE asic flow while sweeping the following parameters Using command "python coffe.py -i 1 input_files/strtx_III_dsp/dsp_coffe_params.txt"
Period (1.53, 2.0, 2.5)
Utilization (0.85, 0.9, 0.95)
metal_layers (5,6,7,8)
dsp_mode (0,1)
wire_load_model (WireAreaLowkAgr)

-Ran the full custom flow to make sure it worked: All results are under ~/COFFE/analyze_results/results_archive

Compared results against those in https://dl.acm.org/doi/10.1145/3301298 (COFFE 2) (they looked reasonable to me, cost looked pretty much like the Agr wire load model presented)

vaughnbetz / COFFE