StephenMoreOSU
commented
3 weeks ago Hi @faaiqgwaqar, I'm currently unsure of the state of the FPGA architecture file generation in this repo at this time. I suspect that if you want to make sure that architecture file generation works (at this moment), you probably have to write the architecture file yourself in the format specified in the vtr documentation.
In the master on this repo there is support for either pass transistor or transmission gate based switches.
As for passing power details from the output of COFFE into VTR the reference can be found here, look under the absolute heading as I think it's what you're looking for.
It's important to know that the power is being estimated at 250MHz, this could be changed manually through modification of the spice simulation code, but if using the existing methodology, I would suspect that this could lead to an underestimate of power consumption if running a design with an intended higher clock frequency.
As for the accuracy of this method of power estimation I would probably defer to @vaughnbetz to see what his thoughts are.
Hello COFFE team, In a few of the works from this lab (examples: Should FPGAS abandon the pass-gate?, FPGA Architecture: Principles and Progression), it seems that there is a way to take the generated power estimation of circuits developed in HSPICE/COFFE and translate them into system power consumption in VPR, however from the VPR documentation and COFFE documentation, it seems unclear how this is done. Is this a built in feature, or is it computed outside of the program? If it is the latter, will there be support for direct translation between the two in the future?
Thanks