Verilator 5 Released

[wsnyder]

Verilator 5.002 2022-10-29

Major:

• This is a major new release.
• Require C++20 for the new --timing features. Upgrading to a C++20 or newer compiler is strongly recommended.
• Support the Active and NBA scheduling regions as defined by the SystemVerilog standard (IEEE 1800-2017 chapter 4). This means all generated clocks are now simulated correctly (verilator/verilator#3278, verilator/verilator#3384). [Geza Lore, Shunyao CAD]
• Support timing controls (delays, event controls in any location, wait statements) and forks. [Krzysztof Bieganski, Antmicro Ltd] This may require adding --timing or --no-timing. See docs for details.
• Introduce a new combinational logic optimizer (DFG), that can yield significant performance improvements on some designs. [Geza Lore, Shunyao CAD]
• Add --binary option as alias of --main --exe --build --timing (verilator/verilator#3625). For designs where C++ was only used to make a simple no-I/O testbench, we recommend abandoning that C++, and instead letting Verilator build it with --binary (or --main).

Minor:

• Split UNUSED warning into genvar, param, and signal warnings (verilator/verilator#3607). [Topa Topino]
• Support standalone 'this' in classes (verilator/verilator#2594) (verilator/verilator#3248) (verilator/verilator#3675). [Arkadiusz Kozdra, Antmicro Ltd]
• Support tristate select/extend (verilator/verilator#3604). [Ryszard Rozak, Antmicro Ltd>
• Support linting for top module interfaces (verilator/verilator#3635). [Kanad Kanhere]
• Support virtual interfaces (verilator/verilator#3654). [Arkadiusz Kozdra, Antmicro Ltd]
• Support class type params without defaults (verilator/verilator#3693). [Krzysztof Bieganski, Antmicro Ltd]
• Support empty generate_regions (verilator/verilator#3695). [mpb27]
• Support access to constructs inside type parameters (verilator/verilator#3702). [Arkadiusz Kozdra, Antmicro Ltd]
• Add --dump-tree-dot to enable dumping Ast Tree .dot files (verilator/verilator#3636). [Marcel Chang]
• Add --get-supported to determine what features are in Verilator.
• Add error on real edge event control.
• Fix false LATCH warning on 'unique if' (verilator/verilator#3088). [Rachit Nigam]
• Fix cell assigning integer array parameters (verilator/verilator#3299). [Michael Platzer]
• Fix LSB error on --hierarchical submodules (verilator/verilator#3539). [danbone]
• Fix $display of fixed-width numbers (verilator/verilator#3565). [Iztok Jeras]
• Fix foreach and pre/post increment in functions (verilator/verilator#3613). [Nandu Raj]
• Fix linker errors in user-facing timing functions (verilator/verilator#3657). [Krzysztof Bieganski, Antmicro Ltd]
• Fix null access on optimized-out fork statements (verilator/verilator#3658). [Krzysztof Bieganski, Antmicro Ltd]
• Fix VPI inline module naming mismatch (verilator/verilator#3690) (verilator/verilator#3694). [Jiuyang Liu]
• Fix deadlock in timeprecision when using systemC (verilator/verilator#3707). [Kamil Rakoczy, Antmicro Ltd]
• Fix width mismatch on inside operator (verilator/verilator#3714). [Alex Torregrosa]