verilator generates incorrect C++ code when genvar is used incorrectly

[veripoolbot]

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Author Name: Alex Solomatnikov Original Redmine Issue: 408 from https://www.veripool.org Original Date: 2011-10-28

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Verilog test case:

`define SIZE  512
`define WIDTH (`SIZE/2)

module e_flop #(parameter WIDTH=1)
    (
     output reg  [WIDTH-1:0] o,
     input  wire [WIDTH-1:0] i,
     input  wire clk,
     input  wire en
     );

    always_ff @(posedge clk)
      if (en)
        o <= i;

endmodule // e_flop

module top
  (
    output logic [`SIZE-1:0] dram_rdata_flopped,
    input logic [`WIDTH-1:0] dram_rdata,
    input logic              dram_rdata_v,
    input logic              clk,
    input logic              rst
    );

    genvar                    i;

    e_flop #(`WIDTH) u_dram_rdata_ff0( .o (dram_rdata_flopped[i*`WIDTH +: `WIDTH]),
                                       .en(dram_rdata_v),
                                       .i (dram_rdata),
                                       .* );
    generate
       for( i=1; i<2; i++ ) begin: STAGING_FF
          e_flop #(`WIDTH) u_dram_rdata_ff( .o (dram_rdata_flopped[i*`WIDTH +: `WIDTH]),
                                            .en(dram_rdata_v),
                                            .i (dram_rdata),
                                            .* );
       end
    endgenerate

endmodule // top

Verilator runs without errors:

verilator -sv -cc --top-module top test.v

Generated code does not compile:

make -f Vtop.mk
/usr/bin/perl /tools/verilator/verilator-3.821/share/verilator/bin/verilator_includer Vtop.cpp > Vtop__ALLcls.cpp
g++44  -I. -MMD -I/tools/verilator/verilator-3.821/share/verilator/include -I/tools/verilator/verilator-3.821/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0        -c -o Vtop__ALLcls.o Vtop__ALLcls.cpp
In file included from Vtop__ALLcls.cpp:2:
Vtop.cpp: In constructor ‘Vtop::Vtop(const char*)’:
Vtop.cpp:25: error: ‘v__DOT__i’ was not declared in this scope
Vtop.cpp: In static member function ‘static void Vtop::_sequent__TOP__1(Vtop__Syms*)’:
Vtop.cpp:138: error: ‘struct Vtop’ has no member named ‘v__DOT__i’
Vtop.cpp:140: error: ‘struct Vtop’ has no member named ‘v__DOT__i’
In file included from Vtop__ALLcls.cpp:2:
Vtop.cpp: In static member function ‘static void Vtop::_settle__TOP__2(Vtop__Syms*)’:
Vtop.cpp:165: error: ‘struct Vtop’ has no member named ‘v__DOT__i’
Vtop.cpp:167: error: ‘struct Vtop’ has no member named ‘v__DOT__i’
make: *** [Vtop__ALLcls.o] Error 1

VCS prints error message.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2012-03-10T00:37:51Z

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Tried to fix quickly but hit annoying issues; genvars may remain as attributes and may be assigned as variables so can't simply check for the AstVarRef disappearing; instead would need to check underneath all possible assignments. Added failing test case to git as t_genvar_misuse_bad.v

[veripoolbot]

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Original Redmine Comment Author Name: Alex Solomatnikov Original Date: 2012-03-10T07:09:47Z

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Certainly a low priority issue. It's just annoying - erroneous Verilog causes C++ errors.