Is it possible to access the member of a user-defined struct in SystemVerilog using VPI and verilator?

[yulong-lan]

In SystemVerilog, we can use our own user-defined data structure, as the example below:

typedef struct packed {
    logic [riscv::VLEN-1:0]   pc;            
    logic [TRANS_ID_BITS-1:0] trans_id;         
    logic [REG_ADDR_SIZE-1:0] rs1;           
    logic [REG_ADDR_SIZE-1:0] rs2;           
    logic [REG_ADDR_SIZE-1:0] rd;           
    riscv::xlen_t             result;          
} scoreboard_entry_t;

For now, we don't need to know what exactly these members represent. What we can see is a user-defined data strucuture in SystemVerilog. And later we instantiate this struct as an input port in a module:

input scoreboard_entry_t issue_instr_i/*verilator public_flat_rd*/,

As above, issue_instr_i is of this data struct and it is exposed to verilator. When I try to access it via VPI:

vpiHandle issue_instr =vpi_handle_by_name((PLI_BYTE8*)"TOP.core.issue_instr_i", NULL);
s_vpi_value v1;
v1.format = vpiHexStrVal;
vpi_get_value(issue_instr, &v1);
printf("instruction: %s\n", v1.value.str);

Apparently it only gives me a long string of hexadecimal values. And if I try to access one of the members with a new VPI handle:

vpiHandle issue_instr =vpi_handle_by_name((PLI_BYTE8*)"TOP.core.issue_instr_i.rs1", NULL);

I get the error message

/...verilator/include/verilated_vpi.cpp:1763: vpi_get_value: Unsupported vpiHandle ((nil))

Could anyone let me know how to access a specific member in this struct? Does Verilator support this?

[wsnyder]

Verilator VPI doesn't support structure member access. I'm marking this answered rather than open as I suspect this won't be supported for a long time, and #860 partially covers this too. If you want to support this we'd accept a pull to add it, but it may have a compile time cost (for designs which have a lot of packed structures which many do).

Note a packed array by definition is represented as a single value internally and in all simulators.