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verilator / verilator

Verilator open-source SystemVerilog simulator and lint system
https://verilator.org
GNU Lesser General Public License v3.0
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seg. fault and %Error: ...: Unsupported tristate port expression: CONST '1'h0' #494

Closed veripoolbot closed 12 years ago

veripoolbot commented 12 years ago

Author Name: Alex Solomatnikov Original Redmine Issue: 494 from https://www.veripool.org Original Date: 2012-04-26 Original Assignee: Wilson Snyder (@wsnyder)

backtrace:

%Error: ...: Unsupported tristate port expression: CONST '1'h0'

Program received signal SIGSEGV, Segmentation fault.
0x0000000000479e8a in AstNodeVarRef::varp (this=0x0) at ../V3Ast.h:1323
1323        AstVar* varp() const { return m_varp; }             // [After Link] Pointer to variable
(gdb) bt
#0  0x0000000000479e8a in AstNodeVarRef::varp (this=0x0) at ../V3Ast.h:1323
#1  0x0000000000618efc in TristateVisitor::visit (this=0x7fffffffa470, nodep=0x49e4920) at ../V3Tristate.cpp:556
#2  0x00000000004942e1 in AstPin::accept (this=0x49e4920, v=..., vup=0x0) at ../V3AstNodes.h:1027
#3  0x0000000000488f7f in AstNode::iterateAndNext (this=0x49e3670, v=..., vup=0x0) at ../V3Ast.cpp:776
#4  0x0000000000488dd1 in AstNode::iterateChildren (this=0x49e7a30, v=..., vup=0x0) at ../V3Ast.cpp:757
#5  0x000000000061add2 in TristateVisitor::visit (this=0x7fffffffa470, nodep=0x49e7a30) at ../V3Tristate.cpp:787
#6  0x000000000049496b in AstCell::accept (this=0x49e7a30, v=..., vup=0x0) at ../V3AstNodes.h:1107
#7  0x0000000000488f7f in AstNode::iterateAndNext (this=0x49de440, v=..., vup=0x0) at ../V3Ast.cpp:776
#8  0x0000000000488df9 in AstNode::iterateChildren (this=0x49de5b0, v=..., vup=0x0) at ../V3Ast.cpp:758
#9  0x00000000006195ab in TristateVisitor::visit (this=0x7fffffffa470, nodep=0x49de5b0) at ../V3Tristate.cpp:608
#10 0x0000000000477edf in AstNVisitor::visit (this=0x7fffffffa470, nodep=0x49de5b0, vup=0x0) at ./V3Ast__gen_visitor.h:117
#11 0x000000000042b81b in AstModule::accept (this=0x49de5b0, v=..., vup=0x0) at ../V3AstNodes.h:1046
#12 0x0000000000489046 in AstNode::iterateListBackwards (this=0xc9a15d0, v=..., vup=0x0) at ../V3Ast.cpp:794
#13 0x00000000004890cc in AstNode::iterateChildrenBackwards (this=0xab8bc0, v=..., vup=0x0) at ../V3Ast.cpp:802
#14 0x000000000061ae0c in TristateVisitor::visit (this=0x7fffffffa470, nodep=0xab8bc0) at ../V3Tristate.cpp:792
#15 0x0000000000475ddb in AstNetlist::accept (this=0xab8bc0, v=..., vup=0x0) at ../V3AstNodes.h:4183
#16 0x000000000061b004 in TristateVisitor::TristateVisitor (this=0x7fffffffa470, nodep=0xab8bc0) at ../V3Tristate.cpp:808
#17 0x000000000061460a in V3Tristate::tristateAll (nodep=0xab8bc0) at ../V3Tristate.cpp:820
#18 0x000000000046fd0f in process () at ../Verilator.cpp:245
#19 0x000000000047491c in main (argc=212, argv=0x7fffffffb2b8, env=0x7fffffffb960) at ../Verilator.cpp:668

    asyncram    asyncram_component (
                .address_a (wraddress),
                .clock0 (clock),
                .data_a (data),
                .wren_a (wren),
                .address_b (rdaddress),
                .q_b (sub_wire0),
                .aclr0 (1'b0),

where aclr0 is declared as:

     input  aclr0;
...
     tri0 aclr0;
veripoolbot commented 12 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2012-04-26T02:54:16Z

Coredump is fixed in git.

The error remains for the moment. While this specific case (0 at the top and zero below, presuming there are no other drivers) is not a conflict, I am not sure I can support the more generic case of a 0 tieoff (supply) at the top and other logic below, since strengths are not implemented. Will give it more thought.

veripoolbot commented 12 years ago

Original Redmine Comment Author Name: Alex Solomatnikov Original Date: 2012-04-26T04:30:58Z

I thought that tri1/tri0 work as pull-up/pull-down, i.e. if the net is not driven then it would have 1/0 value instead of x.

In this case the input is declared as tri0, so it should be 0 if not driven.

If it is assigned to constant, then it should have the value of that constant, i.e. if it was assigned to constant 1, then it should always have value of 1. Isn't this correct?

veripoolbot commented 12 years ago

Original Redmine Comment Author Name: Alex Solomatnikov Original Date: 2012-04-26T05:35:20Z

After seg. fault fix I got:

%Error: ...: Output port is connected to a constant pin, electrical short

on exactly the same line, even though the pin is declared as input, not output.

veripoolbot commented 12 years ago

Original Redmine Comment Author Name: Alex Solomatnikov Original Date: 2012-04-26T05:39:26Z

It seems that in this case and in #, # verilator considers tri0/tri1 inputs as outputs.

veripoolbot commented 12 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2012-04-27T01:12:21Z

Fixed in git. Closing as related to recent tristate changes.