Bit selection from enum causes internal error

[veripoolbot]

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Author Name: Jonathon Donaldson Original Redmine Issue: 951 from https://www.veripool.org Original Date: 2015-08-04 Original Assignee: Wilson Snyder (@wsnyder)

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Taking a slice of an enum generates an internal error:

     ENUM_VAL = 7'h33
  } MyEnum;

  assign out1 = ENUM_VAL[0];

Named values of an enumeration should act like constants so the above code should work fine. The error message is:

Example is attached in test_regress format.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-08-12T12:32:32Z

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This is not supported by VCS, nor NC-verilog so I don't believe Verilator should support it either.

[veripoolbot]

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Original Redmine Comment Author Name: Jonathon Donaldson Original Date: 2015-08-12T18:11:10Z

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So I just did my own checking and Quartus (Altera), Vivado (Xilinx), Synplify (Synopsys), Design Compiler (Synopsys), Questa (Mentor), and Active-HDL (Aldec) all support this feature. So VCS and NC-verilog are definitely in the minority. And to be honest, those simulators really should support this feature.

In addition, it is defined in the standard that enumeration names should be treated similarly to constants - which is why you should be able to take slices of them (since you can most definitely take slices of constants).

Not having this feature is a particular pain right now because we are using enumerated types for specific addresses of register sets in a microprocessor design and we are having to declare both the enumerated list of names and a set of fixed constants (parameters) with the exact same values, which is completely silly. And I imagine this is a perfect example of why the standard allows you to take a slice of an enumeration in the first place. An enumeration really is a constant but the primary difference is the tool is doing the numbering for you.

Is there absolutely no way that you will fix this? Even if I say pretty please with a cherry on top? :) It is supported by all of the synthesis tools that I currently have access to - I think that's worth something.

[veripoolbot]

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Original Redmine Comment Author Name: Jonathon Donaldson Original Date: 2015-08-12T20:35:17Z

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A few more thoughts. First, Microsemi/Actel also supports taking slices of enumerations since they use Synplify. So that's 4 FPGA vendors that support this for synthesis. Additionally, it occurred to me after my first post that Xilinx Vivado and the latest version of Quartus are now using the Verific parser (http://www.verific.com/) for synthesis. So if Quartus and Vivado both support this then it means that Verific supports this feature. Which in turn means that any tools using verific for their SV language parsing also support taking slices of enumerations. According to the Verific home page this would include at least the following additional tools to the ones that I already listed which support this syntax:

Achronix          - ACE
Aldec             - HES
Altera            - Quartus II
Altium            - Nexar
Apache            - Power Theater/Power Artist
Atrenta           - Bugscope
Ausdia            - TimeVision
Blue Pearl        - RTL Analysis
Bull              - Bull Equivalence Checker
Cadence           - CellMath Designer/JasperGold
Calypto           - SLEC, PowerPro
CLKDA             - Amber
Concept           - Engineering   RTLVision PRO
DeFacTo           - STAR, SIGNOFF
Dolphin           - Smash
Excellicon        - ConMan
Flexras           - WASGA
HDL Works         - HDL Companion
Infineon          - Inway
iRoC              - SoCFIT
Lattice           - ispLEVER
Menta             - Origami Designer
Mentor            - Clarus
RealTime          - Designer
Microsemi         - Libero
NEC               - CyberWorkBench
NXP Semiconductor - RTL DfT
Real Intent       - Ascent, Meridian
Rocketick         - RocketSim
S2C               - TAI IP
Synopsys          - Certitude/FineSim/Zebu
Tabula            - Stylus
Tiempo            - ACC
vSync Circuits    - vChecker
Vtool             - Environment Builder/VIP Builder
Xilinx            - ISE Design Suite
Yogitech          - fRTools

I've been trying to get the ASIC and FPGA groups at Sandia Labs to incorporate verilator into their design flow. I've been bragging about how good verilator's language support is and that if they can synthesize it then their should be no issues with verilator parsing it. Not being able to take slices of enumerations and requiring people to make duplicate parameter constants is throwing a wrench in the works. I think this would be a valuable feature for verilator to have. So whaddya say? :)

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-08-13T01:34:23Z

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Oh, ok, fixed in git towards 3.875.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-08-13T01:43:54Z

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In 3.876.

[veripoolbot]

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Original Redmine Comment Author Name: Jonathon Donaldson Original Date: 2015-08-13T18:10:58Z

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Wilson Snyder is THE MAN!! Works perfectly!! THANK YOU THANK YOU THANK YOU! :) :) :) :)

[veripoolbot]

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Original Redmine Comment Author Name: Jonathon Donaldson Original Date: 2015-08-15T02:00:54Z

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I just noticed there was one comment line you forgot to change. Patch attached.

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2015-08-16T15:48:59Z

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Thanks, similar patch applied - want a note so when I run tests against VCS will know it is/was unsupported by them.