verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Nand gate 1 bit error #1338

Closed emacdo12 closed 4 years ago

emacdo12 commented 4 years ago

Expected Behaviour

If a nand gate is called upon, it should produce the appropriate output based on it's inputs.

Current Behaviour

An error occurs while parsing. This is actually an issue with the compiler directives not nand gate. However, it's odd because the errors don't occur with any other gate.

Possible Solution

Steps to Reproduce

This bug is replicated in a PR I made that includes benchmarks for gates (binary). Specifically, nand_wire.vh.

The error is:

 Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)
Email: jamieson.peter@gmail.com and ken@unb.ca for support issues

Using Lut input width of: -1
Verilog: nand_wire.vh
--------------------------------------------------------------------
High-level synthesis Begin
Parser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)
Adding file regression_test/benchmark/verilog/binary/nand_wire.vh to parse list
Adding file "wire_test.v" to parse list
Warning::PARSE_TO_AST wire_test.v:1 error in parsing: (syntax error, unexpected vAND, expecting vSYMBOL_ID or '#')
Optimizing module by AST based optimizations
Error::PARSE_TO_AST Parser found (1) errors in your syntax, exiting
/home/emacdo12/workspace/vtr-verilog-to-routing/ODIN_II/SRC/odin_error.cpp:27: void verify_delayed_error(odin_error): Fatal error
Aborted (core dumped)
GLOBAL_SIM_BASE_CLK a b 
0 0 0 
0 0 1
0 1 0
0 1 1
out
1
1
1
0
`define BINARY_OP(out,a,b) nand(out, a, b);
`include "wire_test.v"
/*
 * Standardized wire test
*/

`ifdef UNARY_OP
    `define OP(out,a) `UNARY_OP(out, a)
`elsif BINARY_OP
    `define OP(out,a,b) `BINARY_OP(out, a, b)
`endif 

`ifdef UNARY_OP 
    module simple_op(a,out);
    input  a;
    output out;

    `OP(out,a)
    endmodule

`elsif BINARY_OP
    module simple_op(a,b,out);
    input  a;
    input  b;
    output out;

    `OP(out,a,b)
    endmodule

`endif

Context

Just a little bug that needs to be fixed.

Your Environment

jeanlego commented 4 years ago

could you link to the file here to be able to reproduce

jeanlego commented 4 years ago

this is actually a preprocessor error. closing