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verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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LUT input pin swapability #157

Open berbagci opened 7 years ago

berbagci commented 7 years ago

So VPR reorders LUT inputs, is there a way to turn this off? I'm particularly interested in turning this feature off for one of the inputs, the input that can be directly connected to FF (input selection mux from one of the LUT inputs to FF input). This is supported by the generic architecture described in original VPR paper.

Let's say LUT input C is also connected to FF input (FF input selection mux). The problem is when inputs are reordered, the input for FF (in some cases) seems to be connected to some other LUT input (e.g. D) which in fact has no connection.

So I would like to prevent VPR from doing that since this is not described in the arch file.

kmurray commented 7 years ago

This sounds like a bug.

Do you have an example circuit and architecture which exhibit the issue?

berbagci commented 7 years ago

I'm attaching the files. The folder has both an example circuit and architecture. Thanks dua_sample.v.zip

berbagci commented 7 years ago

Sorry, the previous folder has all the intermediate files from vtr task as well this one has only the circuit and arch.

example.zip

berbagci commented 7 years ago

so could you replicate the issue? thanks