verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Issue around equivalent port pins #1620

Open mkurc-ant opened 3 years ago

mkurc-ant commented 3 years ago

VPR crashes in some circumstances during static timing analysis after routing. This happens for architectures in which individual port pins that are equivalent ("full" equivalence) are connected using direct instead of complete interconnect.

Expected Behaviour

VPR flow completes successfully.

Current Behaviour

After routing VPR crashes on the assertion: vpr/src/util/vpr_utils.cpp:610 find_pb_route_clb_input_net_pin: Assertion 'pb_routes[next_pb_pin_id].atom_net_id == pb_routes[sink_pb_pin_id].atom_net_id' failed (Connected pb_routes should connect the same net).

Setting equivalent to none temporarily solves the issue.

Possible Solution

?

I believe that the structure pb_routes inside the find_pb_route_clb_input_net_pin function does not reflect correctly how equivalent inputs are modeled (a single SINK node with capacity > 1).

Steps to Reproduce

  1. Use arch.xml and counter.eblif from the included archive: files.tar.gz
  2. Run VPR with the following command: vpr arch.xml counter.eblif --device 4x4 --max_router_iterations 500 --routing_failure_predictor off --router_high_fanout_threshold -1 --constant_net_method route --route_chan_width 50 --clock_modeling ideal --pack --place --route

Context

There is an ongoing effort to use OpenFPGA architectures in SymbiFlow.

The included arch.xml is one of OpenFPGA architectures which were manually adjusted to be supported by the current upstream VPR. The original OpenFPGA architecture is https://github.com/lnis-uofu/SOFA/blob/master/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml.

Your Environment

VPR revision:

Version: 8.1.0-dev+93af9f19d
Revision: v8.0.0-3001-g93af9f19d
Compiled: 2020-12-28T14:57:39
Compiler: GNU 7.4.0 on Linux-4.15.0-45-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2
tangxifan commented 3 years ago

May be this is another limitation of the post-routing synchronization than #1578 . Currently, the pin equivalence is applicable only when

In SOFA architecture, we have only part of LUT inputs equivalent, which caused the problem.