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Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Assertion 'parent_pb->mode == pb_graph_node->pb_type->parent_mode->index' failure #1655

Closed mkurc-ant closed 3 years ago

mkurc-ant commented 3 years ago

Recently I've encountered the assertion failure during clustering: vpr/src/pack/cluster.cpp:1437 try_place_atom_block_rec: Assertion 'parent_pb->mode == pb_graph_node->pb_type->parent_mode->index' failed.

I've spent some time debugging the code and I've roughly narrowed the problem down. For some reason child_pbs together with a selected mode of a pb are not cleared correctly. Those are allocated and set as packer tries to place an atom. Every time a placement fails those should be cleared but in rare cases they are not.

The same assertion gets triggered in some cases for architectures with disabled modes (with disable_packing = "true"). The packer allocates pb and its child_pbs for such modes and bails out later.

Expected Behaviour

Packer should either succeed or fail but without triggering assertions.

Current Behaviour

The assertion 'parent_pb->mode == pb_graph_node->pb_type->parent_mode->index' at `vpr/src/pack/cluster.cpp:1437 try_place_atom_block_rec gets triggered.

Possible Solution

Add (or fix?) cleanup code that removes child_pbs created during atom placement if it fails for any reason.

Steps to Reproduce

Use arch.xml and design.blif from the design.tar.gz archive. Run VPR with the following command:

vpr arch.xml design.blif --device ql-openfpga-k4_N8 --constant_net_method route --route_chan_width 60 --clock_modeling ideal --pack

It will trigger the assertion: vpr/src/pack/cluster.cpp:1449 try_place_atom_block_rec: Assertion 'pb->pb_graph_node == pb_graph_node' failed. which is not the same as the one reported in the issue but the underlying problem is likely the same.

Context

I've been working for supporting a VPR architecture that is used in the OpenFPGA project in SymbiFlow (https://github.com/lnis-uofu/SOFA/blob/master/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml)

Your Environment

tangxifan commented 3 years ago

If it is related to the disable_in_packing, I am the author of that part. I am glad to help on this issue

mkurc-ant commented 3 years ago

@tangxifan It is related to that but not only to. I've been able to trigger the issue even with no disabled modes in the arch. However, the bug is pretty hard to trigger. It showed up in a couple of QuickLogic test designs.

If you run VPR with the architecture and circuit I've attached (design.tar.gz) you will see that it fails during packing a .latch into the io pb_type (there are registered IOs in the arch). This is the "k4_N8" arch from SOFA processed to be used with SymbiFlow.

tangxifan commented 3 years ago

@mkurc-ant No worries. I managed to reproduce this error in other OpenFPGA architectures.