verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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[ODIN] Enable users to provide a pragma to decide how to infer a 2d array #1705

Open aman26kbm opened 3 years ago

aman26kbm commented 3 years ago

Moving an email discussion to a github issue for better tracking.

[Seyed] Previously, every array of registers considered as an implicit memory block. By last changes, a threshold has been considered for inference of implicit memory blocks. That means if the size of register array (or previously depth of the implicit memory block) is less than the threshold, Odin does not infer the array of registers as implicit memory block. Instead, it infers individual registers in size of array size. For the threshold, I have added a new option to Odin executable file. Indeed, by running Odin you can pass "--implicit_memory_threshold YOUR_DESIRED_THRESHOLD" as an argument to Odin. Lastly, the default threshold has considered 128. It worth mentioning that the given implicit memory threshold will be rounded up to the closet power of 2.

[Aman] Regarding the threshold... It is possible that we need a really large register sets, but the threshold for memory generation could be different (say 512 bits). So, I think it'd be also good to have a pragma that can be specified per declaration. That is, a user could do something like the following to indicate what they want. If no pragma is provided, then the default behavior will get deployed (ie. memory unless less than threshold).

pragma generate_memory

reg [15:0] myarr2 [63:0];

OR

pragma generate_registers

reg [15:0] myarr2 [63:0];

Most commercial tools support this kinda thing.

[Seyed] That is an interesting idea. Thank you for mentioning it. I absolutely consider it in future development. Actually, the scenario you mentioned is completely true; we cannot force a user to choose between having a reg array with a specific size or, in contrast having an implicit memory block while they can have both at the same time.

@sdamghan , @KennethKent FYI. Filing this as a future enhancement request.

vaughnbetz commented 3 years ago

Suggest investigating the Xilinx, Synopsys and Intel pragmas and trying to align with at least one of them.