VPR failed when running with the architecture description file that comes with VTR in COFFE_22nm

[jdzhu19]

Expected Behaviour

VPR should be successful

Current Behaviour

When I use the arch in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml and benchmark in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/doc/src/quickstart/blink.v as the input to run vtr by instruction:

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py \
$VTR_ROOT/doc/src/quickstart/blink.v \
$VTR_ROOT/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml \
--route_chan_width 300 \
--max_router_iterations 500

, VPR failed because

stratix10_arch/blink            Error: Executable vpr failed
returncode  :  6
log file    :  vpr.out
failed: Executable vpr failed (took 0.38 seconds, overall memory peak 53.22 MiB consumed by vpr run)

When I use the arch in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml and benchmark in https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/benchmarks/verilog/koios/conv_layer.v as the input to run vtr by instruction:

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py \
$VTR_ROOT/vtr_flow/benchmarks/verilog/koios/conv_layer.v \
$VTR_ROOT/vtr_flow/arch/COFFE_22nm/stratix10_arch.xml \
--route_chan_width 300 \
--max_router_iterations 500

, VPR failed because

stratix10_arch/conv_layer               Error: Executable vpr failed
returncode  :  6
log file    :  vpr.out
failed: Executable vpr failed (took 224.19 seconds, overall memory peak 537.79 MiB consumed by vpr run)

Meanwhile, a large number of Failed route at end, repack cluster trying detailed routing at each stage. occur in vpr.out, and also in vpr.out, it says VTR/vpr/src/pack/post_routing_pb_pin_fixup.cpp:747 update_cluster_regular_routing_traces_with_post_routing_results: Assertion 'is_single_fanout_pb_pin(const_cast<const t_pb_graph_pin*>(new_sink_pb_pin_to_add))' failed.

Here is the vpr.out files mentioned above. vpr_out.zip

But when I use some other benchmarks like https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/timing/EArch.xml and https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/xilinx/simple-7series.xml and various benchmarks to run vtr with appropriate command line parameters, everything is fine in most cases.

Possible Solution

Steps to Reproduce

Use the arch files and design files linked above.

Context

I want to use COFFE to export the architecture description file for input into VTR, but I get failures and errors when testing the architecture description file that comes with VTR in https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/arch/COFFE_22nm .

Your Environment

• VTR revision used: Latest master branch
• Operating System and version:
• Compiler version:

[luck-codeer]

May I ask if you have resolved this issue? I have also encountered a similar problem.

[vaughnbetz]

@MohamedEldafrawy : this is an architecture from your MASc. Any ideas?

[jdzhu19]

May I ask if you have resolved this issue? I have also encountered a similar problem.

To be honest, this is the problem I encountered when I was new to this project, so it has been so long that I forgot how to solve it at that time, but what is certain is that this combination can run through the CAD flow. Maybe you can try to use vtr_task method to run them.

[vaughnbetz]

@StephenMoreOSU : not sure if you remember the fix. It would be good to integrate ...

[StephenMoreOSU]

@tangxifan This looks to be an error in the post routing netlist / clustering fixup. Can you or someone on your team take a look? Thanks :)

[StephenMoreOSU]

@kimiatkh I heard you may have hit this issue as well

[luck-codeer]

When encountering such an issue, one might consider using the command "../scripts/run_vtr_task.py power/power_nofrac_22nm" as an alternative solution.

[OlinLai]

When encountering such an issue, one might consider using the command "../scripts/run_vtr_task.py power/power_nofrac_22nm" as an alternative solution.

Hi, I also met with problem of stratix10_arch.xml but I am a little bit confused about your alternative solution. Running this command "../scripts/run_vtr_task.py power/power_nofrac_22nm" means using another architecture.

So are you saying that when we want to use stratix10_arch.xml, we need to use run_vtr_task.py instead of run_vtr_flow.py? Because when I use run_vtr_task.py, I still encounter the same routing failure as with run_vtr_flow.py.

Also, I would like to ask, does run_vtr_task.py use Yosys or Odin+ABC as the synthesis tool?

Thanks for your @luck-codeer help!

[luck-codeer]

Well, what I meant is to conduct the experiment using .xml in run_task.py, not with stratix10_arch.xml. Also, I believe it will use the corresponding synthesis tool. Here are some of the results of its execution. I hope it will help you.