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Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Change RRG storage to keep (drive pt, direction) instead of (start, end) #2491

Open duck2 opened 4 months ago

duck2 commented 4 months ago

The current expansion pruning in the router uses the drive point of every RRNode ((xlow ,ylow) for non-directional nodes). This check is inside a hot loop (in connection_router.cpp), so there may be performance benefits to store (xdrive, ydrive, dir) in the RRG storage, since the router will only fetch two values instead of three + a branch.

For bidir wires (xdrive, ydrive) can be just (xlow, ylow).

rs-dhow commented 3 weeks ago

If by drive point you mean the coordinate containing the driving mux (for unidir case), note that it's more complex than you write:

  1. if DEC_DIR, (xhigh, yhigh) is the drive point else
  2. if CHANX, (xlow-1, ylow) is the drive point else
  3. (CHANY) (xlow, ylow-1) is the drive point. This is a rather basic property of some fundamental data structures. Is there really a chance this will be changed? The standard at 5 FPGA companies not including Altera was (essentially) to store (driving point, farthest sink) on every wire. The difference between these two was the physical length. (Logical length is the length of the segment TYPE.)