verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
Other
1.02k stars 393 forks source link

Try setting first_iter_pres_fac to a value > 0 #2494

Open vaughnbetz opened 8 months ago

vaughnbetz commented 8 months ago

We might get faster router convergence if the first router iteration paid some attention to routing congestion (both the cost of wiring and any congestion caused by earlier nets).

Proposed Behaviour

Try setting this to 1 (instead of the default 0) and seeing if QoR is unchanged and router time drops (even a little). For the best impact, we should use the criticalities that come from the placer, rather than setting everything to timing-critical, so that code should also be examined.

Current Behaviour

Defaults to 0. Also, we may set all connections to critical in the first iteration (which we'd have to stop doing to have much effect).

vaughnbetz commented 8 months ago

Another possible optimization: don't timing analyze after every router iteration.

vaughnbetz commented 5 months ago

Possibly tuning experiment for you Nathan, at some point.