verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Fix the S10 arch file comments for routing segments and switches #2559

Closed kimiatkh closed 1 month ago

kimiatkh commented 1 month ago

Description

This PR addresses the outdated comments for the routing architecture model of the S10 architecture file. The comments were based on an old version of VPR where different x and y wire segments could not be modeled. The comments have been updated to reflect the new routing model that captures horizontal and vertical routing wires separately.

Types of changes

vaughnbetz commented 1 month ago

Thanks @kimiatkh !