verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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NoC SAT Routing #2564

Closed soheilshahrouz closed 3 weeks ago

soheilshahrouz commented 1 month ago

This PR formulated NoC routing as a SAT problem and invoked cp-sat solver in or-tools to find a deadlock-free solution with the minimum congestion.

Description

Turn model routing algorithms used during annealing generate minimal routes between NoC routers. Congestion may not be resolved with minimal routing. If any NoC link is still congested at the end of the annealing process, we use a SAT solver to find traffic flow routes that minimize congestion while trying to meet latency constraints and prevent the aggregate bandwidth from growing too much.

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vaughnbetz commented 4 weeks ago

@soheilshahrouz : it's worth writing up how you handle the dependence on google OR tools in this PR.