search

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
Other
980 stars 378 forks source link

Router Debug #2569

Closed amin1377 closed 3 weeks ago

amin1377 commented 1 month ago

Description

Fix a bug in router debug print message when node is of the type SOURCE.

If the edge is of the type SOURCE, calling the prev_edge method causes a segmentation fault.