Doc update: mux and wire_switch for segments in arch file

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

https://verilogtorouting.org

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Closed vaughnbetz closed 4 months ago

vaughnbetz commented 4 months ago

Clarified these are defaults only for rr-graph construction and can be overridden in custom switch blocks.

Current text implied to some that this data was crucial in the routing arch, when it is actually just a default for rr-graph construction.