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Specifying a subset of pins in a pin location and causes a segfault #258

Open mithro opened 6 years ago

mithro commented 6 years ago

I'm trying to describe the dual-port ram in the iCE40 (as part of #245). The dual port ram takes up two vertical tiles in the design which you can see described here; image

  <pb_type name="RAM" height="2">
   <!-- Read port -->
   <output name="RDATA" num_pins="16" equivalent="false"/>
   <input  name="RADDR" num_pins="11" equivalent="false"/>
   <input  name="RE"    num_pins="1"  equivalent="false"/>
   <input  name="RCLKE" num_pins="1"  equivalent="false"/>
   <clock  name="RCLK"  num_pins="1"  equivalent="false"/>
   <!-- Write port -->
   <input  name="WDATA" num_pins="16" equivalent="false"/>
   <input  name="MASK"  num_pins="16" equivalent="false"/>
   <input  name="WADDR" num_pins="11" equivalent="false"/>
   <input  name="WE"    num_pins="1"  equivalent="false"/>
   <input  name="WCLKE" num_pins="1"  equivalent="false"/>
   <clock  name="WCLK"  num_pins="1"  equivalent="false"/>
  </pb_type>

The IceStorm docs for the ram tile then describes the "pin layout" as shown here; image

When I describe the architecture with the following, I get a segfault;

   <interconnect>
    <!-- Read port -->
    <direct name="RDATA" input="SB_RAM.RDATA[15:0]" output="RAM.RDATA[15:0]"/>
    <direct name="RADDR" input="RAM.RADDR[7:0]"  output="SB_RAM.RADDR[7:0]" />
    <direct name="RE"    input="RAM.RE"          output="SB_RAM.RE" />
    <direct name="RCLKE" input="RAM.RCLKE"       output="SB_RAM.RCLKE" />
    <direct name="RCLK"  input="RAM.RCLK"        output="SB_RAM.RCLK" />
    <!-- Write port -->
    <direct name="WDATA" input="RAM.WDATA[15:0]" output="SB_RAM.WDATA[15:0]"/>
    <direct name="MASK"  input="RAM.MASK[15:0]"  output="SB_RAM.MASK[15:0]"/>
    <direct name="WADDR" input="RAM.WADDR[7:0]"  output="SB_RAM.WADDR[7:0]" />
    <direct name="WE"    input="RAM.WE"          output="SB_RAM.WE" />
    <direct name="WCLKE" input="RAM.WCLKE"       output="SB_RAM.WCLKE" />
    <direct name="WCLK"  input="RAM.WCLK"        output="SB_RAM.WCLK" />
   </interconnect>

   <fc default_in_type="frac" default_in_val="0.0" default_out_type="frac" default_out_val="0.0">
    <!-- Connect all the ports to 2 local tracks -->
    <fc_override fc_type="abs" fc_val="2" port_name="RDATA" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RADDR" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RE"    segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RCLKE" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RCLK"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WDATA" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="MASK"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WADDR" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WE"    segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WCLKE" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WCLK"  segment_name="local"/>
   </fc>

   <pinlocations pattern="custom">
    <!-- RAMB Tile -->
    <loc side="right" xoffset="0" yoffset="0">
     RAM.RDATA[7:0]
     RAM.WADDR[10:0]
     RAM.MASK[7:0]
     RAM.WDATA[7:0]
     RAM.WCLKE
     RAM.WCLK
     RAM.WE
    </loc>
    <!-- RAMT Tile -->
    <loc side="right" xoffset="0" yoffset="1">
     RAM.RDATA[15:8]
     RAM.RADDR[10:0]
     RAM.MASK[15:8]
     RAM.WDATA[15:8]
     RAM.RCLKE
     RAM.RCLK
     RAM.RE
    </loc>
   </pinlocations>
   <switchblock_locations pattern="external_full_internal_straight"/>
(gdb) bt
#0  __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51
#1  0x00007ffff62513fa in __GI_abort () at abort.c:89
#2  0x0000555555a1d610 in vtr::Assert::handle_assert (expr=0x555555d9f981 "ofs < length", file=0x555555d9f730 "/home/mithro/foss/vtr-verilog-to-routing/vpr/src/route/rr_graph2.cpp", line=899, 
    function=0x555555da02c0 <is_cblock(int, int, int, t_seg_details const*)::__func__> "is_cblock", msg=0x0) at /home/mithro/foss/vtr-verilog-to-routing/libs/libvtrutil/src/vtr_assert.h:108
#3  0x0000555555b0d480 in is_cblock (chan=4, seg=18, track=13794, seg_details=0x5555562241b0) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/route/rr_graph2.cpp:899
#4  0x0000555555b0ce00 in get_bidir_opin_connections (i=4, j=18, ipin=67, edge_list=0x7fffffff2778, opin_to_track_map=std::vector of length 4, capacity 4 = {...}, Fc=2, L_rr_edge_done=0x55555728ebe0, 
    L_rr_node_indices=std::vector of length 7, capacity 7 = {...}, seg_details=0x5555562241b0) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/route/rr_graph2.cpp:783
#5  0x0000555555af9e04 in build_bidir_rr_opins (i=4, j=17, side=RIGHT, L_rr_node=0x7ffff4009018, L_rr_node_indices=std::vector of length 7, capacity 7 = {...}, opin_to_track_map=std::vector of length 4, capacity 4 = {...}, 
    Fc_out=std::vector of length 4, capacity 4 = {...}, L_rr_edge_done=0x55555728ebe0, seg_details=0x5555562241b0, grid=..., directs=0x0, num_directs=0, clb_to_clb_directs=0x0, num_seg_types=4)
    at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/route/rr_graph.cpp:1168
#6  0x0000555555af97a5 in alloc_and_load_rr_graph (num_nodes=51036, L_rr_node=0x7ffff4009018, num_seg_types=4, seg_details=0x5555562241b0, chan_details_x=..., chan_details_y=..., L_rr_edge_done=0x55555728ebe0, 
    track_to_pin_lookup=std::vector of length 4, capacity 4 = {...}, opin_to_track_map=std::vector of length 4, capacity 4 = {...}, switch_block_conn=..., sb_conn_map=0x55555729dca0, grid=..., Fs=3, sblock_pattern=0x0, 
    Fc_out=std::vector of length 4, capacity 4 = {...}, Fc_xofs=..., Fc_yofs=..., L_rr_node_indices=std::vector of length 7, capacity 7 = {...}, max_chan_width=172, delayless_switch=2, directionality=BI_DIRECTIONAL, 
    wire_to_ipin_switch=1, Fc_clipped=0x7fffffff2a6f, directs=0x0, num_directs=0, clb_to_clb_directs=0x0) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/route/rr_graph.cpp:1074
#7  0x0000555555af6d3b in build_rr_graph (graph_type=GRAPH_BIDIR, L_num_types=4, types=0x55555616c178, grid=..., nodes_per_chan=0x55555613e5a8 <g_vpr_ctx+168>, sb_type=CUSTOM, Fs=3, 
    switchblocks=std::vector of length 3, capacity 3 = {...}, num_seg_types=4, num_arch_switches=3, segment_inf=0x55555616aea0, global_route_switch=2, delayless_switch=2, wire_to_arch_ipin_switch=1, R_minW_nmos=6065.52002, 
    R_minW_pmos=18138.5, base_cost_type=DELAY_NORMALIZED, trim_empty_channels=false, trim_obs_channels=false, directs=0x0, num_directs=0, dump_rr_structs_file=0x0, wire_to_rr_ipin_switch=0x7fffffffc034, 
    num_rr_switches=0x55555613e608 <g_vpr_ctx+264>, Warnings=0x7fffffff323c) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/route/rr_graph.cpp:572
#8  0x0000555555af5a2e in create_rr_graph (graph_type=GRAPH_BIDIR, num_block_types=4, block_types=0x55555616c178, grid=..., nodes_per_chan=0x55555613e5a8 <g_vpr_ctx+168>, num_arch_switches=3, det_routing_arch=0x7fffffffc000, 
    segment_inf=0x55555616aea0, base_cost_type=DELAY_NORMALIZED, trim_empty_channels=false, trim_obs_channels=false, directs=0x0, num_directs=0, num_rr_switches=0x55555613e608 <g_vpr_ctx+264>, Warnings=0x7fffffff323c)
    at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/route/rr_graph.cpp:296
#9  0x0000555555aafdf7 in alloc_routing_structs (router_opts=..., det_routing_arch=0x7fffffffc000, segment_inf=0x55555616aea0, directs=0x0, num_directs=0)
    at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/place/timing_place_lookup.cpp:241
#10 0x0000555555aaf9e9 in compute_delay_lookup_tables (router_opts=..., det_routing_arch=0x7fffffffc000, segment_inf=0x55555616aea0, chan_width_dist=..., directs=0x0, num_directs=0)
    at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/place/timing_place_lookup.cpp:110
#11 0x0000555555aaf828 in alloc_lookups_and_criticalities (chan_width_dist=..., router_opts=..., det_routing_arch=0x7fffffffc000, segment_inf=0x55555616aea0, directs=0x0, num_directs=0)
    at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/place/timing_place.cpp:89
#12 0x0000555555a967a3 in try_place (placer_opts=..., annealing_sched=..., chan_width_dist=..., router_opts=..., det_routing_arch=0x7fffffffc000, segment_inf=0x55555616aea0, directs=0x0, num_directs=0)
    at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/place/place.cpp:371
#13 0x0000555555a1a4d2 in vpr_place (vpr_setup=..., arch=...) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/base/vpr_api.cpp:505
#14 0x0000555555a1a2bc in vpr_place_flow (vpr_setup=..., arch=...) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/base/vpr_api.cpp:476
#15 0x0000555555a196bc in vpr_flow (vpr_setup=..., arch=...) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/base/vpr_api.cpp:284
#16 0x0000555555a0a745 in main (argc=7, argv=0x7fffffffdbd8) at /home/mithro/foss/vtr-verilog-to-routing/vpr/src/main.cpp:69

If I change the pinlocations to just use a single loc, it works;

   <pinlocations pattern="custom">
    <loc side="right" xoffset="0" yoffset="0">
     RAM.RDATA[15:0]
     RAM.RADDR[10:0]
     RAM.RE
     RAM.RCLKE
     RAM.RCLK
     RAM.WDATA[15:0]
     RAM.MASK[15:0]
     RAM.WADDR[10:0]
     RAM.WE
     RAM.WCLKE
     RAM.WCLK
    </loc>
   </pinlocations>

If I change the fc_override values to be split up, it seems to stop the segfault;

   <interconnect>
    <!-- Read port -->
    <direct name="RDATA" input="SB_RAM.RDATA[15:0]" output="RAM.RDATA[15:0]"/>
    <direct name="RADDR" input="RAM.RADDR[7:0]"  output="SB_RAM.RADDR[7:0]" />
    <direct name="RE"    input="RAM.RE"          output="SB_RAM.RE" />
    <direct name="RCLKE" input="RAM.RCLKE"       output="SB_RAM.RCLKE" />
    <direct name="RCLK"  input="RAM.RCLK"        output="SB_RAM.RCLK" />
    <!-- Write port -->
    <direct name="WDATA" input="RAM.WDATA[15:0]" output="SB_RAM.WDATA[15:0]"/>
    <direct name="MASK"  input="RAM.MASK[15:0]"  output="SB_RAM.MASK[15:0]"/>
    <direct name="WADDR" input="RAM.WADDR[7:0]"  output="SB_RAM.WADDR[7:0]" />
    <direct name="WE"    input="RAM.WE"          output="SB_RAM.WE" />
    <direct name="WCLKE" input="RAM.WCLKE"       output="SB_RAM.WCLKE" />
    <direct name="WCLK"  input="RAM.WCLK"        output="SB_RAM.WCLK" />
   </interconnect>

   <fc default_in_type="frac" default_in_val="0.0" default_out_type="frac" default_out_val="0.0">
    <!-- Connect all the ports to 2 local tracks -->
    <fc_override fc_type="abs" fc_val="2" port_name="RDATA[7:0]" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RDATA[15:8]" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RADDR[10:0]" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RE"    segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RCLKE" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RCLK"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WDATA[7:0]" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WDATA[15:8]" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="MASK[7:0]"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="MASK[15:8]"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WADDR[10:0]" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WE"    segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WCLKE" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WCLK"  segment_name="local"/>
   </fc>

   <pinlocations pattern="custom">
    <!-- RAMB Tile -->
    <loc side="right" xoffset="0" yoffset="0">
     RAM.RDATA[7:0]
     RAM.WADDR[10:0]
     RAM.MASK[7:0]
     RAM.WDATA[7:0]
     RAM.WCLKE
     RAM.WCLK
     RAM.WE
    </loc>
    <!-- RAMT Tile -->
    <loc side="right" xoffset="0" yoffset="1">
     RAM.RDATA[15:8]
     RAM.RADDR[10:0]
     RAM.MASK[15:8]
     RAM.WDATA[15:8]
     RAM.RCLKE
     RAM.RCLK
     RAM.RE
    </loc>
   </pinlocations>

But I get the following errors;

Warning 69: in check_rr_node: rr_node 2970 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=58 has no out-going edges.   
Warning 70: in check_rr_node: rr_node 2971 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=59 has no out-going edges.     
Warning 71: in check_rr_node: rr_node 2972 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=60 has no out-going edges.                                                                                                                            
Warning 72: in check_rr_node: rr_node 2973 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=61 has no out-going edges.     
Warning 73: in check_rr_node: rr_node 2974 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=62 has no out-going edges.   
Warning 74: in check_rr_node: rr_node 2975 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=63 has no out-going edges.     
Warning 75: in check_rr_node: rr_node 2976 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=64 has no out-going edges.                                                                                                                            
Warning 76: in check_rr_node: rr_node 2977 OPIN at (4,2) side=RIGHT, block_type=RAM ptc=65 has no out-going edges.     
Warning 77: in check_rr_node: rr_node 2978 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=66 has no out-going edges.   
Warning 78: in check_rr_node: rr_node 2979 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=67 has no out-going edges.     
Warning 79: in check_rr_node: rr_node 2980 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=68 has no out-going edges.                                                                                                                            
Warning 80: in check_rr_node: rr_node 2981 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=69 has no out-going edges.     
Warning 81: in check_rr_node: rr_node 2982 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=70 has no out-going edges.   
Warning 82: in check_rr_node: rr_node 2983 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=71 has no out-going edges.     
Warning 83: in check_rr_node: rr_node 2984 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=72 has no out-going edges.                                                                                                                            
Warning 84: in check_rr_node: rr_node 2985 OPIN at (4,3) side=RIGHT, block_type=RAM ptc=73 has no out-going edges.     
Warning 85: in check_rr_node: rr_node 3122 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=58 has no out-going edges.   
Warning 86: in check_rr_node: rr_node 3123 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=59 has no out-going edges.     
Warning 87: in check_rr_node: rr_node 3124 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=60 has no out-going edges.                                                                                                                            
Warning 88: in check_rr_node: rr_node 3125 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=61 has no out-going edges.     
Warning 89: in check_rr_node: rr_node 3126 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=62 has no out-going edges.   
Warning 90: in check_rr_node: rr_node 3127 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=63 has no out-going edges.     
Warning 91: in check_rr_node: rr_node 3128 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=64 has no out-going edges.                                                                                                                            
Warning 92: in check_rr_node: rr_node 3129 OPIN at (4,4) side=RIGHT, block_type=RAM ptc=65 has no out-going edges.     
Warning 93: in check_rr_node: rr_node 3130 OPIN at (4,5) side=RIGHT, block_type=RAM ptc=66 has no out-going edges.   
Warning 94: in check_rr_node: rr_node 3131 OPIN at (4,5) side=RIGHT, block_type=RAM ptc=67 has no out-going edges.     
Warning 95: in check_rr_node: rr_node 3132 OPIN at (4,5) side=RIGHT, block_type=RAM ptc=68 has no out-going edges.                                                                                                                            
Warning 96: in check_rr_node: rr_node 3133 OPIN at (4,5) side=RIGHT, block_type=RAM ptc=69 has no out-going edges.     
Warning 97: in check_rr_node: rr_node 3134 OPIN at (4,5) side=RIGHT, block_type=RAM ptc=70 has no out-going edges.   
Warning 98: in check_rr_node: rr_node 3135 OPIN at (4,5) side=RIGHT, block_type=RAM ptc=71 has no out-going edges.     
Warning 99: in check_rr_node: rr_node 3136 OPIN at (4,5) side=RIGHT, block_type=RAM ptc=72 has no out-going edges.                                  
-----
Cannot route from PIO.inpad[0] (rr_node: 1 type: SOURCE ptc: 1 xlow: 1 ylow: 2) to RAM.RADDR[0] (rr_node: 2836 type: SINK ptc: 0 xlow: 4 ylow: 2) to -- no possible path                                                                      
Warning 436: Unable to route between blocks at (1,2) and (4,2) to characterize delay (setting to inf)                  
Warning 437: Empty heap occurred in get_heap_head.                                                                   
Warning 438: Some blocks are impossible to connect in this architecture.                                               
Cannot route from PIO.inpad[0] (rr_node: 1 type: SOURCE ptc: 1 xlow: 1 ylow: 2) to RAM.RADDR[0] (rr_node: 2836 type: SINK ptc: 0 xlow: 4 ylow: 2) to -- no possible path                                                                      
Warning 439: Unable to route between blocks at (1,2) and (4,3) to characterize delay (setting to inf)                  
Warning 440: Empty heap occurred in get_heap_head.                                                                    
Warning 441: Some blocks are impossible to connect in this architecture.                                               
Cannot route from PIO.inpad[0] (rr_node: 1 type: SOURCE ptc: 1 xlow: 1 ylow: 2) to RAM.RADDR[0] (rr_node: 2988 type: SINK ptc: 0 xlow: 4 ylow: 4) to -- no possible path                                                                      
Warning 442: Unable to route between blocks at (1,2) and (4,4) to characterize delay (setting to inf)                  
Warning 443: Empty heap occurred in get_heap_head.

Your Environment

mithro commented 6 years ago

image

mithro commented 6 years ago

So it seems <fc_override fc_type="abs" fc_val="2" port_name="RDATA[7:0]" segment_name="local"/> and <loc side="right" xoffset="0" yoffset="0"> don't take partial pins, you can only specify the full port name. I've reworked the code to;

  <pb_type name="RAM" height="2">
   <!-- Read port -->
   <output name="RDATAT" num_pins="8"  equivalent="false"/>
   <output name="RDATAB" num_pins="8"  equivalent="false"/>
   <input  name="RADDR"  num_pins="11" equivalent="false"/>
   <input  name="RE"     num_pins="1"  equivalent="false"/>
   <input  name="RCLKE"  num_pins="1"  equivalent="false"/>
   <clock  name="RCLK"   num_pins="1"  equivalent="false"/>
   <!-- Write port -->
   <input  name="WDATAT" num_pins="8"  equivalent="false"/>
   <input  name="WDATAB" num_pins="8"  equivalent="false"/>
   <input  name="MASKT"  num_pins="8"  equivalent="false"/>
   <input  name="MASKB"  num_pins="8"  equivalent="false"/>
   <input  name="WADDR"  num_pins="11" equivalent="false"/>
   <input  name="WE"     num_pins="1"  equivalent="false"/>
   <input  name="WCLKE"  num_pins="1"  equivalent="false"/>
   <clock  name="WCLK"   num_pins="1"  equivalent="false"/>

   <fc default_in_type="frac" default_in_val="0.0" default_out_type="frac" default_out_val="0.0">
    <fc_override fc_type="abs" fc_val="2" port_name="RDATAT" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RDATAB" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RADDR"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RE"     segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RCLKE"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="RCLK"   segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WDATAT" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WDATAB" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="MASKT"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="MASKB"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WADDR"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WE"     segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WCLKE"  segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="WCLK"   segment_name="local"/>
   </fc>

   <pinlocations pattern="custom">
    <!-- RAMB Tile -->
    <loc side="right" xoffset="0" yoffset="0">
     RAM.RDATAB
     RAM.WADDR
     RAM.MASKB
     RAM.WDATAB
     RAM.WCLKE
     RAM.WCLK
     RAM.WE
    </loc>
    <!-- RAMT Tile -->
    <loc side="right" xoffset="0" yoffset="1">
     RAM.RDATAT
     RAM.RADDR
     RAM.MASKT
     RAM.WDATAT
     RAM.RCLKE
     RAM.RCLK
     RAM.RE
    </loc>
   </pinlocations>
   <switchblock_locations pattern="external_full_internal_straight"/>
  </pb_type>
  <!-- End RAM -->

But now I'm hitting the following; vtr-verilog-to-routing/vpr/src/route/rr_graph2.cpp:900 is_cblock: Assertion 'ofs < length' failed.

mithro commented 6 years ago 
Type: "RAM"
    capacity: 1
    width: 1
    height: 2
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 0 1 2 3 4 5 6 7 8 9 10
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 11
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 12
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 13 14 15 16 17 18 19 20
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 21 22 23 24 25 26 27 28
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 29 30 31 32 33 34 35 36
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 37 38 39 40 41 42 43 44
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 45 46 47 48 49 50 51 52 53 54 55
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 56
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 57
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 58 59 60 61 62 63 64 65
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 66 67 68 69 70 71 72 73
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 74
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: global pins: 75
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 0 1 2 3 4 5 6 7 8 9 10
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 11
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 12
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 13 14 15 16 17 18 19 20
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 21 22 23 24 25 26 27 28
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 29 30 31 32 33 34 35 36
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 37 38 39 40 41 42 43 44
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 45 46 47 48 49 50 51 52 53 54 55
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 56
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 57
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 58 59 60 61 62 63 64 65
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 66 67 68 69 70 71 72 73
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 74
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span12 pins: 75
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 0 1 2 3 4 5 6 7 8 9 10
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 11
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 12
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 13 14 15 16 17 18 19 20
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 21 22 23 24 25 26 27 28
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 29 30 31 32 33 34 35 36
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 37 38 39 40 41 42 43 44
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 45 46 47 48 49 50 51 52 53 54 55
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 56
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 57
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 58 59 60 61 62 63 64 65
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 66 67 68 69 70 71 72 73
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 74
fc_value_type: FRACTIONAL fc_value: 0.000000 segment: span4 pins: 75
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 0 1 2 3 4 5 6 7 8 9 10
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 11
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 12
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 13 14 15 16 17 18 19 20
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 21 22 23 24 25 26 27 28
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 29 30 31 32 33 34 35 36
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 37 38 39 40 41 42 43 44
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 45 46 47 48 49 50 51 52 53 54 55
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 56
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 57
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 58 59 60 61 62 63 64 65
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 66 67 68 69 70 71 72 73
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 74
fc_value_type: ABSOLUTE fc_value: 2.000000 segment: local pins: 75
    num_drivers: 16
    num_receivers: 58
mithro commented 6 years ago

@kmurray - Any idea what is going on here?

I hit my head against it a bit yesterday but was unable to figure out the correct fix.

FYI When we fix this, then I should have blockrams on the iCE40. If you need more information (like the full arch.xml) I'm happy to provide.

kmurray commented 6 years ago

Full architecture files would help debug the issue. VPR should not crash on invalid input.

A quick look through the code indicates that <fc_override> only supports a single override per port.

I haven't looked at the <loc> handling code, but I think it should support per-pin location specifications.