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verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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[CI] Fixed Issue with Artifacts not Being Saved On Failure #2583

Closed AlexandreSinger closed 4 weeks ago

AlexandreSinger commented 4 weeks ago

Reverted a change I made in PR #2568 which caused the CI to not generate artifacts on failure for the nightly tests.

Added a comment to document what this feature does and prevent this issue for the future.