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verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Update documentation (and code if needed) to make placement constraints 3D #2587

Closed vaughnbetz closed 1 month ago

vaughnbetz commented 3 months ago

VTR now supports 3D devices, but the placement constraints documentation at https://docs.verilogtorouting.org/en/latest/vpr/placement_constraints/ is still 2D.

Proposed Behaviour

Update the example and documentation to 3D. Confirm the code works for 3D devices. Add a regtest for a few 3D placement constraints (e.g. one to a specific x,y,layer, and another to a region of (xlow-->xhigh, ylow-->yhigh, layer_low-->layer_high).

vaughnbetz commented 3 months ago

Also we need a test (can be a small device) with a few 3D constraints.