verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Update documentation for 3D arch switches #2592

Open vaughnbetz opened 3 weeks ago

vaughnbetz commented 3 weeks ago

The wire segment documentation doesn't mention the new mux_inter_die tag. E.g.:

<segment name="L4" freq="260" length="4" type="unidir" Rmetal="201.7" Cmetal="18.0e-15">
  <mux name="seg4_driver"/>
  <mux_inter_die name="seg4_driver"/>
  <!-- L4 connect to connection block L4 and L4prime -->
  <sb type="pattern">1 1 1 1 1</sb>
  <cb type="pattern">1 1 1 1</cb>
</segment>

Proposed Behaviour

We should document this. Optional tag, used for rr-graph creation on 3D architectures where switch block connections can cross dice. Can be overriden by a custom switch block, or ignored if you read in an rr-graph.