Test rr-graph write out and read in with a 3D architecture.

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

https://verilogtorouting.org

Other

979 stars 378 forks source link

Test rr-graph write out and read in with a 3D architecture. #2593

Open vaughnbetz opened 3 weeks ago

vaughnbetz commented 3 weeks ago

We should have a test for this, as we have some new tags (layers) and we also are autocreating a wire segment type for 3D switch blocks. We should have a test for that code path; it can be a very small device.