verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Yosys Update -> Version 0.41[Latest] #2595

Closed amirarjmand93 closed 3 weeks ago

amirarjmand93 commented 3 weeks ago

Description

This update brings Yosys to the latest version, 0.41, which includes several bug fixes, performance improvements, and new features that enhance the synthesis capabilities of our flow. Notable additions in this version include : -New commands and options -Verific support -Added support for using ABCs library -Added support for VHDL 2009

For a detailed list of changes and improvements in Yosys 0.41, please refer to the release notes.

Related Issue

-Update Yosys [The latest version in the VTR flow is 0.32]

Types of changes