verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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[Docs] Updated Profiling VTR Section in Developer Guide #2605

Open ueqri opened 2 weeks ago

ueqri commented 2 weeks ago

Close #2545.

Rewrote the existing Profiling VTR section, specifically the one using GNU gprof tool.

Added another subsection to explain how to use the Linux perf tool to profile VPR and visualize its output.

ueqri commented 2 weeks ago

Expectations:

image

Remaining Issues:

"Some checks haven’t completed yet": It appears to be the issue Alex mentioned in https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2598#issuecomment-2155633380.

A potential issue you may run into is that there are required tests in our PR flow (sets of tests which must succeed in order for the code to be merged in). If the CI does not run for documentation changes, the PR may never be merged since it did not pass the required tests. I am not sure the best way to resolve this issue, but it should be resolved.

Moreover, here is the exact troubleshoot reference from GitHub.

If a workflow is skipped due to path filtering, branch filtering or a commit message, then checks associated with that workflow will remain in a "Pending" state. A pull request that requires those checks to be successful will be blocked from merging.

If, however, a job within a workflow is skipped due to a conditional, it will report its status as "Success". For more information, see "Using conditions to control job execution."

Potential Solutions:

vaughnbetz commented 2 weeks ago

Thanks! Looks good -- just a couple of suggestions.