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verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Use Simple Place Delay Model By Default #2608

Open amin1377 opened 2 weeks ago

amin1377 commented 2 weeks ago

In this PR, the default place delay mode is changed from delt (which runs the router for each dx and dy and stores the minimum cost across sample locations) to simple (which gets the minimum cost for each dx and dy from the information stored in the router lookahead).

amin1377 commented 2 weeks ago

VTR Large:

image
amin1377 commented 2 weeks ago

Titan:

screenshot_2024-06-06_092317
vaughnbetz commented 1 week ago

QoR data for Koios is actually for the placement refactoring ... ignore for this PR.

vaughnbetz commented 1 week ago

@amin1377 : is this good to merge (still a few CI failures)? @nedsels will benefit from the larger QoR tolerances in another PR.