Enable VTR to flush stdout and stderr before assertion

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

https://verilogtorouting.org

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Enable VTR to flush stdout and stderr before assertion #2610

Closed robluo closed 3 months ago

robluo commented 3 months ago

When debugging, I find that sometimes when the program hits an assertion, some log would not be printed as expected. Manually flushing before abort() brings more consistent printing.