Loosen the minimum channel width and related metric pass characteristics for small circuits

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

https://verilogtorouting.org

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Loosen the minimum channel width and related metric pass characteristics for small circuits #2613

Open vaughnbetz opened 2 weeks ago

vaughnbetz commented 2 weeks ago

We get a reasonable number of spurious QoR failures in CI on the small benchmarks in things like arithmetic/figure8. We should loosen the relevant QoR metrics by making new small pass requirements and pointing at them. As circuits fail, we can point the relevant tests at this set of looser criteria instead of constantly updating golden.

This is better practice than having spurious failures that people learn to update -- that takes longer, and teaches a bad habit of expecting some failures.

amin1377 commented 1 week ago

This is implemented in PR #2608.