See if simplifying the placement cost function slightly would speed up placement.

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

https://verilogtorouting.org

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See if simplifying the placement cost function slightly would speed up placement. #2614

Open vaughnbetz opened 2 weeks ago

vaughnbetz commented 2 weeks ago

Try commenting out the crossing count multiplication and channel width normalization to see how much runtime it saves. Neither is a key feature, and both could be removed or simplified if they are taking significant time.