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verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
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legalizer frontend #2615

Closed KA7E closed 1 week ago

KA7E commented 2 weeks ago

Frontend modifications to incorporate legalizer.

Description

vpr_api.cpp:

  1. Added code to invoke the legalizer in vpr_pack_flow as follows: if doPacking=STAGE_LOAD and packer_opts.load_flat_placement=true, this code: a. builds the device grid per a specified fixed device layout b. calls load_flat_place (impl coming soon), which will:
    • load and legalize the input flat placement file
    • print a clustered netlist
    • print a fixed clusters (partial .place) file c. clears the device grid d. if placement will run next, specifies the fixed clusters file as a constraints file. e. resumes normal load packing behavior (load .net file, do various checks)
  2. Added a function call to print a flat placement file after VPR placement

SetupGrid.h: Added default arguments to create_device_grid so that it can be called with a fixed device layout without other args (that are only used when auto-sizing).

read_options.h/cpp: Added the following command line inputs: --legalize, enables the legalizer --flat_place_file , legalizer input file --write_fix_clusters (default: fix_clusters.out), for legalizer placed clusters output --write_flat_place (default: flat_place.out), for post-placement flat placement output

SetupVPR.cpp: Added the following fields to the FileNameOpts data structure:

CheckSetup.cpp:

  1. Added a check that errors out if a fixed device layout is not specified for legalization.
  2. Added a check that errors out if an input constraints file is specified (using --fix_clusters ) when running legalization, since the legalizer will provide cluster placement info.

read_place.h/cpp: Added an optional boolean input to print_place which defaults to true (in which case the function's behavior does not change). If false, the header is not printed, unplaced blocks (loc.x = -1) are skipped, and the net_file and net_id parameters are unused and can be set to nullptr. This is useful if the output will be used as a constraints (fix clusters) file.

added load_flat_place.h/cpp: Function to print a flat placement file. Function to load flat placement (impl coming soon).

Related Issue

Motivation and Context

Incorporates the legalizer.

How Has This Been Tested?

Verified that, if legalizer option is not enabled, vpr runs as usual with no QoR change. The legalization capability has been tested on all Titan23 benchmarks.

Types of changes

Checklist:

KA7E commented 1 week ago

@AlexandreSinger can you help me figure out why these keep failing?

vaughnbetz commented 1 week ago

It looks like memory corruption. I looked at one of the strong regtests, and there are a huge number of failures due to vpr not completing. You can download the raw logs by clicking on the gear icon after clicking on a test:

2024-06-18T12:15:00.0635639Z 12:15:00 | log file : /root/vtr-verilog-to-routing/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/run001/stratixiv_arch.timing.xml/sudoku_check_stratixiv_arch_timing.blif/common/vpr.out

You can see the vpr output by selecting the download log archive from the same gear icon, double clicking on a regression test and opening the big text.txt output file. That shows there is a segmentation fault at the end of placement (signal 11 is a seg fault), e.g.:

2024-06-18T12:05:27.4656365Z <Placement perturbation distribution by block and move type: 2024-06-18T12:05:27.4657772Z <------------------ ----------------- ---------------- ---------------- --------------- ------------ 2024-06-18T12:05:27.4658857Z < Block Type Move Type (%) of Total Accepted(%) Rejected(%) Aborted(%) 2024-06-18T12:05:27.4660073Z <------------------ ----------------- ---------------- ---------------- --------------- ------------ 2024-06-18T12:05:27.4661159Z <io Uniform 11.67 28.57 71.43 0.00
2024-06-18T12:05:27.4662149Z < Median 16.67 10.00 80.00 10.00
2024-06-18T12:05:27.4662998Z < Centroid 8.33 20.00 80.00 0.00
2024-06-18T12:05:27.4663864Z < W. Centroid 40.00 41.67 58.33 0.00
2024-06-18T12:05:27.4664778Z < W. Median 1.67 0.00 100.00 0.00
2024-06-18T12:05:27.4665714Z < Crit. Uniform 3.33 0.00 100.00 0.00
2024-06-18T12:05:27.4666674Z < Feasible Region 1.67 0.00 100.00 0.00
2024-06-18T12:05:27.4667495Z < 2024-06-18T12:05:27.4668064Z <clb Uniform 5.00 0.00 0.00 100.00
2024-06-18T12:05:27.4669003Z < Median 3.33 0.00 0.00 100.00
2024-06-18T12:05:27.4670857Z < W. Centroid 8.33 0.00 0.00 100.00
2024-06-18T12:05:27.4671675Z < 2024-06-18T12:05:27.4672021Z < 2024-06-18T12:05:27.4674310Z <Placement Quench timing analysis took 2.0208e-05 seconds (1.5038e-05 STA, 5.17e-06 slack) (1 full updates: 1 setup, 0 hold, 0 combined). 2024-06-18T12:05:27.4676676Z <Placement Total timing analysis took 0.0011949 seconds (0.00114186 STA, 5.3039e-05 slack) (Command terminated by signal 11 2024-06-18T12:05:27.4680085Z < Command being timed: "/home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing/vpr/vpr k6_N10_mem32K_40nm.xml multiclock --circuit_file multiclock.pre-vpr.blif --net_file ../../../../multiclock.net --verify_file_digests

I suggest running a circuit locally and bringing it up in the debugger to see the call stack, and/or you could run the sanitized build or valgrind.

KA7E commented 1 week ago

Silly me, forgot to delete the old (unconditional) call to print_flat_placement when I moved it inside a function and added a condition. @vaughnbetz can you take a look once CI has finished?

vaughnbetz commented 1 week ago

Looks good; thanks.