legalizer documentation

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

https://verilogtorouting.org

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legalizer documentation #2620

Open KA7E opened 1 week ago

KA7E commented 1 week ago

Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

[ ] Bug fix (change which fixes an issue)
[ ] New feature (change which adds functionality)
[ ] Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

[ ] My change requires a change to the documentation
[ ] I have updated the documentation accordingly
[ ] I have added tests to cover my changes
[ ] All new and existing tests passed

vaughnbetz commented 1 week ago

Looks good; I have a few suggested changes.

KA7E commented 1 week ago

@vaughnbetz for expedience I went ahead and added default flat placement file name generation (in a separate PR). Please review both that PR and this one when CI completes.

vaughnbetz commented 1 week ago

Looks good. i added one more comment for the --legalize option which should be easy to resolve.

vaughnbetz commented 2 days ago

@KA7E Please see the comment above and resolve it so we can get this feature in, as it is described & referenced in a Heart paper now. To merge this documentation, the feature itself needs to work, and the code for that should be added as soon as possible. I believe the remaining items are:

Add the code for the actual flat placement file parsing and calls to the cluster creation API to make the clustering.
Add a few tests.
Make this small documentation update

If there are more updates required please add to this list.