verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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[documentation] added how to debug build vpr documentation #2622

Closed robluo closed 3 months ago

robluo commented 3 months ago

Provided documentation for a simple way to build VPR in debug mode.

vaughnbetz commented 3 months ago

Thanks Robert.